common: remove Port.connect and use 2 separate Record.connect.

examples/targets/udp.py

@@ -26,7 +26,8 @@ class UDPSoC(BaseSoC):
             self.submodules += buf
         else:
             setattr(self.submodules, name, buf)
-        self.comb += Port.connect(port, buf)
+        self.comb += port.source.connect(buf.sink)
+        self.comb += buf.source.connect(port.sink)
 
 # UDPSoCDevel --------------------------------------------------------------------------------------
 

examples/targets/udp_loopback/versa_ecp5.py

@@ -82,8 +82,8 @@ class UDPLoopback(SoCMini):
             self.submodules += buf
         else:
             setattr(self.submodules, name, buf)
-        self.comb += Port.connect(port, buf)
-
+        self.comb += port.source.connect(buf.sink)
+        self.comb += buf.source.connect(port.sink)
 
 # Load ---------------------------------------------------------------------------------------------
 def load():

liteeth/common.py

@@ -14,13 +14,6 @@ from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.packet import Header, HeaderField
 
 
-class Port:
-    def connect(self, port):
-        r = [self.source.connect(port.sink),
-             port.source.connect(self.sink)]
-        return r
-
-
 eth_mtu = 1530
 eth_min_len = 46
 eth_interpacket_gap = 12

liteeth/mac/__init__.py

@@ -41,7 +41,8 @@ class LiteEthMAC(Module, AutoCSR):
                 self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, endianness, hw_mac)
             else:
                 assert dw == 32
-                self.comb += Port.connect(self.interface, self.core)
+                self.comb += self.interface.source.connect(self.core.sink)
+                self.comb += self.core.source.connect(self.interface.sink)
 
     def get_csrs(self):
         return self.csrs