phy/{s7,us}rgmii.py:

Recent modification that adds S7PLL that in return adds an AsyncResetSynchronizer inside XilinxClocking.

This actually creates a multi-driven net because there is another AsyncResetSync* being added in the Phys.

This change instantiates the PLL without a reset for now, leaving the CD reset intact.

liteeth/phy/s7rgmii.py

@@ -118,7 +118,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
         from litex.soc.cores.clock import S7PLL
         self.submodules.pll = pll = S7PLL()
         pll.register_clkin(ClockSignal("eth_rx"), 125e6)
-        pll.create_clkout(self.cd_eth_tx, 125e6)
+        pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False)
         pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase)
 
         eth_tx_clk_obuf = Signal()

liteeth/phy/usrgmii.py

@@ -159,7 +159,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
         from litex.soc.cores.clock import USPLL
         self.submodules.pll = pll = USPLL()
         pll.register_clkin(ClockSignal("eth_rx"), 125e6)
-        pll.create_clkout(self.cd_eth_tx, 125e6)
+        pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False)
         pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase)
 
         eth_tx_clk_obuf = Signal()