phy/usrgmii.py:

IDELAYE3 requires EN_VTC to be enabled for fixed mode time delay. This eliminates implementation time CRITICAL WARNINGs and ensures generating a bitfile.

liteeth/phy/usrgmii.py

@@ -77,7 +77,7 @@ class LiteEthPHYRGMIIRX(Module):
                 i_CNTVALUEIN=0,
                 i_IDATAIN=rx_ctl_ibuf,
                 i_RST=0,
-                i_EN_VTC=0,
+                i_EN_VTC=1,
                 o_DATAOUT=rx_ctl_idelay),
             Instance("IDDRE1",
                 p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
@@ -110,7 +110,7 @@ class LiteEthPHYRGMIIRX(Module):
                     i_CNTVALUEIN=0,
                     i_IDATAIN=rx_data_ibuf[i],
                     i_RST=0,
-                    i_EN_VTC=0,
+                    i_EN_VTC=1,
                     o_DATAOUT=rx_data_idelay[i]),
                 Instance("IDDRE1",
                     p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",