liteeth_gen: Disable wip Etherbone.
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@ -311,7 +311,7 @@ class UDPCore(PHYCore):
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# Etherbone --------------------------------------------------------------------------------
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# Etherbone --------------------------------------------------------------------------------
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# /!\ WIP /!\
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# /!\ WIP /!\
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with_etherbone = True
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with_etherbone = False
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if with_etherbone:
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if with_etherbone:
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assert (data_width == 32)
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assert (data_width == 32)
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys")
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self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys")
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