liteeth_gen: Add initial (and wip) etherbone support.

liteeth/gen.py

@@ -47,6 +47,8 @@ from liteeth import phy as liteeth_phys
 from liteeth.mac import LiteEthMAC
 from liteeth.core import LiteEthUDPIPCore
 
+from liteeth.frontend.etherbone import LiteEthEtherbone
+
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
@@ -306,6 +308,19 @@ class UDPCore(PHYCore):
             with_sys_datapath = (data_width == 32),
         )
 
+        # Etherbone --------------------------------------------------------------------------------
+
+        # /!\ WIP /!\
+        with_etherbone = True
+        if with_etherbone:
+            assert (data_width == 32)
+            self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, buffer_depth=16, cd="sys")
+            axil_bus = axi.AXILiteInterface(address_width=32, data_width=32)
+            platform.add_extension(axil_bus.get_ios("mmap"))
+            self.submodules += axi.Wishbone2AXILite(self.etherbone.wishbone.bus, axil_bus)
+            self.comb += axil_bus.connect_to_pads(platform.request("mmap"), mode="master")
+         # /!\ WIP /!\
+
         # UDP Ports --------------------------------------------------------------------------------
         for name, port in core_config["udp_ports"].items():
             # Parameters.