usp_1000basex: Update a few parameter and add debug probes to investigate on xcu1525.
This commit is contained in:
Florent Kermarrec
parent
a57178ac26
commit
f00d95c534
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@ -63,6 +63,9 @@ class BenchSoC(SoCCore):
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ident_version = True
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)
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# UARTBone ---------------------------------------------------------------------------------
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self.add_uartbone()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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@ -70,7 +73,7 @@ class BenchSoC(SoCCore):
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self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk,
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data_pads = self.platform.request("qsfp", 0),
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sys_clk_freq = self.clk_freq)
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self.comb += self.platform.request("qsfp_fs").eq(0b01)
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#self.comb += self.platform.request("qsfp_fs").eq(0b01)
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# SRAM -------------------------------------------------------------------------------------
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@ -80,7 +83,22 @@ class BenchSoC(SoCCore):
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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sys_clk_freq = sys_clk_freq
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)
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# Litescope --------------------------------------------------------------------------------
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from litescope import LiteScopeAnalyzer
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analyzer_signals = self.ethphy.debug
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 256,
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clock_domain = "sys",
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csr_csv = "analyzer.csv"
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)
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# Main ---------------------------------------------------------------------------------------------
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@ -646,8 +646,6 @@ class KU_1000BASEX(Module, AutoCSR):
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i_RXUSERRDY = 0b1,
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i_RXUSRCLK2 = ClockSignal("eth_rx_half"),
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i_RXUSRCLK = ClockSignal("eth_rx_half"),
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#i_SATA_BURST = 0b100,
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#i_SATA_EIDLE = 0b100,
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i_SIGVALIDCLK = 0b0,
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i_TSTIN = 0b00000000000000000000,
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i_TX8B10BBYPASS = 0b00000000,
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@ -153,8 +153,8 @@ class USP_1000BASEX(Module, AutoCSR):
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p_CLK_COR_SEQ_1_ENABLE = 0b1111,
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p_CLK_COR_SEQ_2_1 = 0b0010111100,
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p_CLK_COR_SEQ_2_2 = 0b0010110101,
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p_CLK_COR_SEQ_2_3 = 0b0000000000,
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p_CLK_COR_SEQ_2_4 = 0b0000000000,
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p_CLK_COR_SEQ_2_3 = 0b0100000000,
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p_CLK_COR_SEQ_2_4 = 0b0100000000,
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p_CLK_COR_SEQ_2_ENABLE = 0b1111,
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p_CLK_COR_SEQ_2_USE = "TRUE",
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p_CLK_COR_SEQ_LEN = 2,
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@ -213,7 +213,7 @@ class USP_1000BASEX(Module, AutoCSR):
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p_ES_SDATA_MASK7 = 0b0000000000000000,
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p_ES_SDATA_MASK8 = 0b0000000000000000,
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p_ES_SDATA_MASK9 = 0b0000000000000000,
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p_EYESCAN_VP_RANGE = 0,
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p_EYESCAN_VP_RANGE = 0b0,
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p_EYE_SCAN_SWAP_EN = 0b0,
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p_FTS_DESKEW_SEQ_ENABLE = 0b1111,
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p_FTS_LANE_DESKEW_CFG = 0b1111,
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@ -398,7 +398,7 @@ class USP_1000BASEX(Module, AutoCSR):
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p_RXSLIDE_MODE = "OFF",
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p_RXSYNC_MULTILANE = 0b0,
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p_RXSYNC_OVRD = 0b0,
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p_RXSYNC_SKIP_DA = 0b0,
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p_RXSYNC_SKIP_DA = 0b1,
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p_RX_AFE_CM_EN = 0b0,
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p_RX_BIAS_CFG0 = 0b0001001010110000,
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p_RX_BUFFER_CFG = 0b000000,
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@ -464,7 +464,9 @@ class USP_1000BASEX(Module, AutoCSR):
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p_SAMPLE_CLK_PHASE = 0b0,
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p_SAS_12G_MODE = 0b0,
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p_SATA_BURST_SEQ_LEN = 0b1111,
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p_SATA_BURST_VAL = 0b100,
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p_SATA_CPLL_CFG = "VCO_3000MHZ",
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p_SATA_EIDLE_VAL = 0b100,
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p_SHOW_REALIGN_COMMA = "TRUE",
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p_SIM_DEVICE = "ULTRASCALE_PLUS",
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p_SIM_MODE = "FAST",
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@ -504,6 +506,7 @@ class USP_1000BASEX(Module, AutoCSR):
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p_TXPI_PPM = 0b0,
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p_TXPI_PPM_CFG = 0b00000000,
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p_TXPI_SYNFREQ_PPM = 0b001,
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p_TXPMARESET_TIME = 0b00011,
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p_TXREFCLKDIV2_SEL = 0b0,
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p_TXSWBST_BST = 1,
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p_TXSWBST_EN = 0,
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@ -598,7 +601,7 @@ class USP_1000BASEX(Module, AutoCSR):
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i_CPLLLOCKDETCLK = 0b0,
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i_CPLLLOCKEN = 0b1,
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i_CPLLPD = pll_reset,
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i_CPLLREFCLKSEL = 0b001,
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i_CPLLREFCLKSEL = 0b111,
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i_CPLLRESET = 0b0,
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i_DMONFIFORESET = 0b0,
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i_DMONITORCLK = 0b0,
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@ -807,7 +810,7 @@ class USP_1000BASEX(Module, AutoCSR):
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i_TXPOSTCURSOR = 0b00000,
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i_TXPRBSFORCEERR = 0b0,
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i_TXPRBSSEL = 0b0000,
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i_TXPRECURSOR =0b00000,
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i_TXPRECURSOR = 0b00000,
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i_TXPROGDIVRESET = 0b0,
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i_TXRATE = 0b000,
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i_TXRATEMODE = 0b0,
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@ -984,3 +987,18 @@ class USP_1000BASEX(Module, AutoCSR):
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gearbox.tx_data.eq(pcs.tbi_tx),
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pcs.tbi_rx.eq(gearbox.rx_data)
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]
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self.debug = [
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gtpowergood,
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pll_reset,
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pll_locked,
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tx_reset,
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tx_data,
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tx_reset_done,
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rx_reset,
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rx_data,
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rx_reset_done,
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self.sink,
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self.source,
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self.link_up
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]
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