phy/s6rgmii: improve presentation
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0cf9c2057d
commit
8fb0dae18a
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@ -16,7 +16,7 @@ class LiteEthPHYRGMIITX(Module):
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# # #
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tx_ctl_obuf = Signal()
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tx_ctl_obuf = Signal()
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tx_data_obuf = Signal(4)
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self.specials += [
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@ -89,14 +89,14 @@ class LiteEthPHYRGMIIRX(Module):
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# # #
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rx_ctl_ibuf = Signal()
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rx_ctl_idelay = Signal()
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rx_ctl = Signal()
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rx_ctl_reg = Signal()
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rx_data_ibuf = Signal(4)
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rx_ctl_ibuf = Signal()
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rx_ctl_idelay = Signal()
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rx_ctl = Signal()
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rx_ctl_reg = Signal()
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rx_data_ibuf = Signal(4)
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rx_data_idelay = Signal(4)
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rx_data = Signal(8)
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rx_data_reg = Signal(8)
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rx_data = Signal(8)
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rx_data_reg = Signal(8)
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self.specials += [
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Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
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@ -243,8 +243,8 @@ class LiteEthPHYRGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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