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liteeth_gen: Allow configuring TX/RX delay RGMII PHYs.

This commit is contained in:
Florent Kermarrec 2021-07-16 17:50:37 +02:00
parent 72dd7bf283
commit 947ed03720
1 changed files with 3 additions and 1 deletions
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4
liteeth/gen.py
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@ -198,6 +198,8 @@ class PHYCore(SoCMini):
ethphy = phy( ethphy = phy(
clock_pads = platform.request("rgmii_eth_clocks"), clock_pads = platform.request("rgmii_eth_clocks"),
pads = platform.request("rgmii_eth"), pads = platform.request("rgmii_eth"),
tx_delay = core_config.get("phy_tx_delay", 2e-9),
rx_delay = core_config.get("phy_rx_delay", 2e-9),
with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk. with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
else: else:
raise ValueError("Unsupported PHY") raise ValueError("Unsupported PHY")
@ -299,7 +301,7 @@ def main():
core_config[k] = replaces[r] core_config[k] = replaces[r]
if k == "phy": if k == "phy":
core_config[k] = getattr(liteeth_phys, core_config[k]) core_config[k] = getattr(liteeth_phys, core_config[k])
if k == "clk_freq": if k in ["clk_freq", "phy_tx_delay", "phy_rx_delay"]:
core_config[k] = int(float(core_config[k])) core_config[k] = int(float(core_config[k]))
# Generate core -------------------------------------------------------------------------------- # Generate core --------------------------------------------------------------------------------