use mininal imports

example_designs/targets/etherbone.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
+from liteeth.frontend.etherbone import LiteEthEtherbone
 
 from targets.base import BaseSoC
-from liteeth.frontend.etherbone import LiteEthEtherbone
 
 
 class EtherboneSoC(BaseSoC):

example_designs/targets/tty.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
+from liteeth.frontend.tty import LiteEthTTY
 
 from targets.base import BaseSoC
-from liteeth.frontend.tty import LiteEthTTY
 
 
 class TTYSoC(BaseSoC):

example_designs/targets/udp.py

@@ -1,5 +1,7 @@
 from liteeth.common import *
 
+from litex.soc.interconnect.stream_packet import Buffer
+
 from targets.base import BaseSoC
 
 

liteeth/common.py

@@ -1,16 +1,12 @@
-import math
-from collections import OrderedDict
+from math import ceil
 
 from litex.gen import *
-from litex.gen.genlib.resetsync import AsyncResetSynchronizer
-from litex.gen.genlib.record import *
-from litex.gen.genlib.fsm import FSM, NextState
-from litex.gen.genlib.misc import chooser, WaitTimer
 
 from litex.soc.interconnect.stream import *
-from litex.soc.interconnect.stream_packet import *
 from litex.soc.interconnect.csr import *
 
+from litex.soc.interconnect.stream_packet import Header, HeaderField
+
 
 def reverse_bytes(signal):
     n = (len(signal)+7)//8

liteeth/core/arp.py

@@ -1,5 +1,8 @@
 from liteeth.common import *
 
+from litex.gen.genlib.misc import WaitTimer
+from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer
+
 
 _arp_table_layout = [
         ("reply", 1),

liteeth/core/icmp.py

@@ -1,5 +1,8 @@
 from liteeth.common import *
 
+from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer, Buffer
+
+
 # icmp tx
 
 class LiteEthICMPPacketizer(Packetizer):

liteeth/core/ip.py

@@ -1,6 +1,9 @@
 from liteeth.common import *
 from liteeth.crossbar import LiteEthCrossbar
 
+from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer
+
+
 # ip crossbar
 
 class LiteEthIPV4MasterPort:

liteeth/core/mac/common.py

@@ -1,6 +1,8 @@
 from liteeth.common import *
 from liteeth.crossbar import LiteEthCrossbar
 
+from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer
+
 
 class LiteEthMACDepacketizer(Depacketizer):
     def __init__(self):

liteeth/core/mac/core/crc.py

@@ -1,7 +1,10 @@
-from liteeth.common import *
 from functools import reduce
 from operator import xor
+from collections import OrderedDict
 
+from liteeth.common import *
+
+from litex.gen.genlib.misc import chooser, WaitTimer
 
 
 class LiteEthMACCRCEngine(Module):

liteeth/core/mac/core/gap.py

@@ -7,7 +7,7 @@ class LiteEthMACGap(Module):
 
         # # #
 
-        gap = math.ceil(eth_interpacket_gap/(dw//8))
+        gap = ceil(eth_interpacket_gap/(dw//8))
         counter = Signal(max=gap)
         counter_reset = Signal()
         counter_ce = Signal()

liteeth/core/mac/core/padding.py

@@ -8,7 +8,7 @@ class LiteEthMACPaddingInserter(Module):
 
         # # #
 
-        padding_limit = math.ceil(padding/(dw/8))-1
+        padding_limit = ceil(padding/(dw/8))-1
 
         counter = Signal(16, reset=1)
         counter_done = Signal()

liteeth/core/mac/core/preamble.py

@@ -1,5 +1,7 @@
 from liteeth.common import *
 
+from litex.gen.genlib.misc import chooser
+
 
 class LiteEthMACPreambleInserter(Module):
     def __init__(self, dw):

liteeth/core/udp.py

@@ -1,6 +1,9 @@
 from liteeth.common import *
 from liteeth.crossbar import LiteEthCrossbar
 
+from litex.soc.interconnect.stream_packet import Depacketizer, Packetizer, Buffer
+
+
 # udp crossbar
 
 class LiteEthUDPMasterPort:

liteeth/crossbar.py

@@ -2,6 +2,9 @@ from collections import OrderedDict
 
 from liteeth.common import *
 
+from litex.soc.interconnect.stream_packet import Arbiter, Dispatcher
+
+
 class LiteEthCrossbar(Module):
     def __init__(self, master_port, dispatch_param):
         self.users = OrderedDict()

liteeth/frontend/etherbone.py

@@ -1,6 +1,7 @@
 from liteeth.common import *
 
 from litex.soc.interconnect import wishbone
+from litex.soc.interconnect.stream_packet import *
 
 # etherbone packet
 

liteeth/phy/gmii.py

@@ -1,7 +1,8 @@
-from litex.gen.genlib.io import DDROutput
-
 from liteeth.common import *
 
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+
 
 class LiteEthPHYGMIITX(Module):
     def __init__(self, pads, pads_register=True):

liteeth/phy/gmii_mii.py

@@ -1,12 +1,13 @@
+from liteeth.common import *
+from liteeth.phy.gmii import LiteEthPHYGMIICRG
+from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
+
 from litex.gen.genlib.io import DDROutput
 from litex.gen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import Multiplexer, Demultiplexer
 
-from liteeth.common import *
-from liteeth.phy.gmii import LiteEthPHYGMIICRG
-from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
 modes = {
     "GMII": 0,

liteeth/phy/mii.py

@@ -1,5 +1,7 @@
 from liteeth.common import *
 
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+
 
 def converter_description(dw):
     payload_layout = [("data", dw)]

liteeth/phy/rmii.py

@@ -1,5 +1,7 @@
 from liteeth.common import *
 
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+
 
 def converter_description(dw):
     payload_layout = [("data", dw)]

liteeth/phy/s6rgmii.py

@@ -1,10 +1,11 @@
 # RGMII PHY for Spartan-6
+from liteeth.common import *
 
 from litex.gen.genlib.io import DDROutput
 from litex.gen.genlib.misc import WaitTimer
 from litex.gen.genlib.fsm import FSM, NextState
 
-from liteeth.common import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
 
 
 class LiteEthPHYRGMIITX(Module):