mac/core: Introduce TX/RXDatapath modules to simplify code.
This commit is contained in:
Florent Kermarrec
parent
11555d43cb
commit
a4a070af4d
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@ -28,8 +28,8 @@ class LiteEthMACCore(Module, AutoCSR):
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self.source = stream.Endpoint(eth_phy_description(dw))
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# Parameters.
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self.core_dw = core_dw = dw
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self.phy_dw = phy_dw = phy.dw
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core_dw = dw
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phy_dw = phy.dw
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if core_dw < phy_dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy_dw))
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@ -45,164 +45,159 @@ class LiteEthMACCore(Module, AutoCSR):
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# CSRs.
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if with_preamble_crc:
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self.preamble_crc = CSRStatus(reset=1)
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self.preamble_errors = CSRStatus(32)
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self.crc_errors = CSRStatus(32)
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# TX Data-Path (Core --> PHY).
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# ------------------------------------------------------------------------------------------
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self.tx_datapath = tx_datapath = []
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class TXDatapath(Module, AutoCSR):
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def __init__(self):
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self.pipeline = []
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# Sink.
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tx_datapath.append(self.sink)
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# Late sys conversion.
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if not with_sys_datapath:
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self.add_tx_converter()
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# Padding.
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if with_padding:
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tx_padding = padding.LiteEthMACPaddingInserter(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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tx_padding = ClockDomainsRenamer(cd_tx)(tx_padding)
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self.submodules += tx_padding
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tx_datapath.append(tx_padding)
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# Preamble / CRC.
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if with_preamble_crc:
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# CRC insert.
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tx_crc = crc.LiteEthMACCRC32Inserter(eth_phy_description(datapath_dw))
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tx_crc = BufferizeEndpoints({"sink": DIR_SINK})(tx_crc) # FIXME: Still required?
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tx_crc = ClockDomainsRenamer(cd_tx)(tx_crc)
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self.submodules += tx_crc
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tx_datapath.append(tx_crc)
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# Preamble insert.
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tx_preamble = preamble.LiteEthMACPreambleInserter(datapath_dw)
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tx_preamble = ClockDomainsRenamer(cd_tx)(tx_preamble)
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self.submodules += tx_preamble
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tx_datapath.append(tx_preamble)
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# Interpacket gap.
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tx_gap = gap.LiteEthMACGap(datapath_dw)
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tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap)
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self.submodules += tx_gap
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tx_datapath.append(tx_gap)
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# Early sys conversion.
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if with_sys_datapath:
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self.add_tx_converter(core_dw, phy_dw)
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# PHY.
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tx_datapath.append(phy)
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# Data-Path.
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self.submodules.tx_pipeline = stream.Pipeline(*tx_datapath)
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# RX Data-Path (PHY --> Core).
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# ------------------------------------------------------------------------------------------
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self.rx_datapath = rx_datapath = []
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# PHY.
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rx_datapath.append(phy)
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# Early sys conversion.
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if with_sys_datapath:
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self.add_rx_converter()
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# Preamble / CRC.
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if with_preamble_crc:
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# Preamble check.
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rx_preamble = preamble.LiteEthMACPreambleChecker(datapath_dw)
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rx_preamble = ClockDomainsRenamer(cd_rx)(rx_preamble)
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self.submodules += rx_preamble
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rx_datapath.append(rx_preamble)
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# Preamble error counter.
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self.submodules.ps_preamble_error = PulseSynchronizer(cd_rx, "sys")
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self.comb += self.ps_preamble_error.i.eq(rx_preamble.error)
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self.sync += [
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If(self.ps_preamble_error.o,
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self.preamble_errors.status.eq(self.preamble_errors.status + 1))
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]
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# CRC check.
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rx_crc = crc.LiteEthMACCRC32Checker(eth_phy_description(datapath_dw))
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rx_crc = BufferizeEndpoints({"sink": DIR_SINK})(rx_crc) # FIXME: Still required?
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rx_crc = ClockDomainsRenamer(cd_rx)(rx_crc)
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self.submodules += rx_crc
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rx_datapath.append(rx_crc)
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# CRC error counter.
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self.submodules.ps_crc_error = PulseSynchronizer(cd_rx, "sys")
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self.comb += self.ps_crc_error.i.eq(rx_crc.error),
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self.sync += [
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If(self.ps_crc_error.o,
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self.crc_errors.status.eq(self.crc_errors.status + 1)
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)
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]
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# Padding.
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if with_padding:
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rx_padding = padding.LiteEthMACPaddingChecker(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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rx_padding = ClockDomainsRenamer(cd_rx)(rx_padding)
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self.submodules += rx_padding
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rx_datapath.append(rx_padding)
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# Late sys conversion.
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if not with_sys_datapath:
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self.add_rx_converter()
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# Source.
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rx_datapath.append(self.source)
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# Data-Path.
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self.submodules.rx_pipeline = stream.Pipeline(*rx_datapath)
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def add_tx_converter(self):
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def add_converter(self):
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# CHECKME: Order probably needs to be adapted based on core_dw/phy_dw ratio.
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# Cross Domain Crossing.
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(self.core_dw),
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
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cd_from = "sys",
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cd_to = "eth_tx",
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depth = 32)
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self.submodules += tx_cdc
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self.tx_datapath.append(tx_cdc)
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self.pipeline.append(tx_cdc)
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# Converters.
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if self.core_dw != self.phy_dw:
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if core_dw != phy_dw:
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tx_converter = stream.StrideConverter(
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description_from = eth_phy_description(self.core_dw),
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description_to = eth_phy_description(self.phy_dw))
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description_from = eth_phy_description(core_dw),
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description_to = eth_phy_description(phy_dw))
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tx_converter = ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += tx_converter
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self.tx_datapath.append(tx_converter)
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self.pipeline.append(tx_converter)
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# Delimiters.
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if self.core_dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(self.phy_dw)
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if core_dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy_dw)
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tx_last_be = ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += tx_last_be
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self.tx_datapath.append(tx_last_be)
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self.pipeline.append(tx_last_be)
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def add_rx_converter(self):
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def add_padding(self):
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tx_padding = padding.LiteEthMACPaddingInserter(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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tx_padding = ClockDomainsRenamer(cd_tx)(tx_padding)
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self.submodules += tx_padding
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self.pipeline.append(tx_padding)
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def add_crc(self):
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tx_crc = crc.LiteEthMACCRC32Inserter(eth_phy_description(datapath_dw))
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tx_crc = BufferizeEndpoints({"sink": DIR_SINK})(tx_crc) # FIXME: Still required?
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tx_crc = ClockDomainsRenamer(cd_tx)(tx_crc)
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self.submodules += tx_crc
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self.pipeline.append(tx_crc)
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def add_preamble(self):
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tx_preamble = preamble.LiteEthMACPreambleInserter(datapath_dw)
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tx_preamble = ClockDomainsRenamer(cd_tx)(tx_preamble)
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self.submodules += tx_preamble
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self.pipeline.append(tx_preamble)
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def add_gap(self):
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tx_gap = gap.LiteEthMACGap(datapath_dw)
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tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap)
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self.submodules += tx_gap
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self.pipeline.append(tx_gap)
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def do_finalize(self):
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self.submodules += stream.Pipeline(*self.pipeline)
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tx_datapath = TXDatapath()
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tx_datapath.pipeline.append(self.sink)
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if not with_sys_datapath:
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tx_datapath.add_converter()
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if with_padding:
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tx_datapath.add_padding()
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if with_preamble_crc:
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tx_datapath.add_crc()
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tx_datapath.add_preamble()
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tx_datapath.add_gap()
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if with_sys_datapath:
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tx_datapath.add_converter()
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tx_datapath.pipeline.append(phy)
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self.submodules.tx_datapath = tx_datapath
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# RX Data-Path (PHY --> Core).
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# ------------------------------------------------------------------------------------------
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class RXDatapath(Module, AutoCSR):
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def __init__(self):
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self.pipeline = []
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if with_preamble_crc:
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self.preamble_errors = CSRStatus(32)
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self.crc_errors = CSRStatus(32)
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def add_preamble(self):
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rx_preamble = preamble.LiteEthMACPreambleChecker(datapath_dw)
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rx_preamble = ClockDomainsRenamer(cd_rx)(rx_preamble)
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self.submodules += rx_preamble
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self.pipeline.append(rx_preamble)
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ps = PulseSynchronizer(cd_rx, "sys")
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self.submodules += ps
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self.comb += ps.i.eq(rx_preamble.error)
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self.sync += If(ps.o, self.preamble_errors.status.eq(self.preamble_errors.status + 1))
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def add_crc(self):
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rx_crc = crc.LiteEthMACCRC32Checker(eth_phy_description(datapath_dw))
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rx_crc = BufferizeEndpoints({"sink": DIR_SINK})(rx_crc) # FIXME: Still required?
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rx_crc = ClockDomainsRenamer(cd_rx)(rx_crc)
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self.submodules += rx_crc
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self.pipeline.append(rx_crc)
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ps = PulseSynchronizer(cd_rx, "sys")
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self.submodules += ps
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self.comb += ps.i.eq(rx_crc.error),
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self.sync += If(ps.o, self.crc_errors.status.eq(self.crc_errors.status + 1))
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def add_padding(self):
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rx_padding = padding.LiteEthMACPaddingChecker(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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rx_padding = ClockDomainsRenamer(cd_rx)(rx_padding)
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self.submodules += rx_padding
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self.pipeline.append(rx_padding)
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def add_converter(self):
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# CHECKME: Order probably needs to be adapted based on core_dw/phy_dw ratio.
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# Delimiters.
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if self.core_dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(self.phy_dw)
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if core_dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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rx_last_be = ClockDomainsRenamer("eth_rx")(rx_last_be)
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self.submodules += rx_last_be
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self.rx_datapath.append(rx_last_be)
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self.pipeline.append(rx_last_be)
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# Converters.
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if self.core_dw != self.phy_dw:
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if core_dw != phy_dw:
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rx_converter = stream.StrideConverter(
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description_from = eth_phy_description(self.phy_dw),
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description_to = eth_phy_description(self.core_dw))
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description_from = eth_phy_description(phy_dw),
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description_to = eth_phy_description(core_dw))
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rx_converter = ClockDomainsRenamer("eth_rx")(rx_converter)
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self.submodules += rx_converter
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self.rx_datapath.append(rx_converter)
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self.pipeline.append(rx_converter)
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# Cross Domain Crossing
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(self.core_dw),
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
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cd_from = "eth_rx",
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cd_to = "sys",
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depth = 32)
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self.submodules += rx_cdc
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self.rx_datapath.append(rx_cdc)
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self.pipeline.append(rx_cdc)
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def do_finalize(self):
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self.submodules += stream.Pipeline(*self.pipeline)
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rx_datapath = RXDatapath()
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rx_datapath.pipeline.append(phy)
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if with_sys_datapath:
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rx_datapath.add_converter()
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if with_preamble_crc:
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rx_datapath.add_preamble()
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rx_datapath.add_crc()
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if with_padding:
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rx_datapath.add_padding()
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if not with_sys_datapath:
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rx_datapath.add_converter()
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rx_datapath.pipeline.append(self.source)
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self.submodules.rx_datapath = rx_datapath
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