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use udp port 1234 for etherbone

This commit is contained in:
Florent Kermarrec 2017-06-22 11:28:45 +02:00
parent e68e2ed73c
commit ad9ecdbd5e
2 changed files with 2 additions and 2 deletions
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2
example_designs/targets/etherbone.py
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@ -10,7 +10,7 @@ class EtherboneSoC(BaseSoC):
BaseSoC.__init__(self, platform, BaseSoC.__init__(self, platform,
mac_address=0x10e2d5000000, mac_address=0x10e2d5000000,
ip_address="192.168.1.50") ip_address="192.168.1.50")
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000, mode="master") self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus) self.add_wb_master(self.etherbone.wishbone.bus)

2
test/test_etherbone.py
View File

@ -24,7 +24,7 @@ class DUT(Module):
self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False) self.submodules.etherbone_model = etherbone.Etherbone(self.udp_model, debug=False)
self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000) self.submodules.core = LiteEthUDPIPCore(self.phy_model, mac_address, ip_address, 100000)
self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 20000) self.submodules.etherbone = LiteEthEtherbone(self.core.udp, 1234)
self.submodules.sram = wishbone.SRAM(1024) self.submodules.sram = wishbone.SRAM(1024)
self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus) self.submodules.interconnect = wishbone.InterconnectPointToPoint(self.etherbone.master.bus, self.sram.bus)