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liteeth
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global: use new StrideConverter

This commit is contained in:
Florent Kermarrec 2016-03-16 17:01:13 +01:00
parent 51f56e79dd
commit aff07c6809
4 changed files with 18 additions and 18 deletions
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12
liteeth/core/mac/core.py
View File

@ -67,12 +67,12 @@ class LiteEthMACCore(Module, AutoCSR):
# Converters # Converters
if dw != phy.dw: if dw != phy.dw:
reverse = endianness == "big" reverse = endianness == "big"
tx_converter = stream.Converter(eth_phy_description(dw), tx_converter = stream.StrideConverter(eth_phy_description(dw),
eth_phy_description(phy.dw), eth_phy_description(phy.dw),
reverse=reverse) reverse=reverse)
rx_converter = stream.Converter(eth_phy_description(phy.dw), rx_converter = stream.StrideConverter(eth_phy_description(phy.dw),
eth_phy_description(dw), eth_phy_description(dw),
reverse=reverse) reverse=reverse)
self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter) self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter) self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)

8
liteeth/core/udp.py
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@ -35,15 +35,15 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
user_port = LiteEthUDPUserPort(dw) user_port = LiteEthUDPUserPort(dw)
internal_port = LiteEthUDPUserPort(8) internal_port = LiteEthUDPUserPort(8)
if dw != 8: if dw != 8:
converter = stream.Converter(eth_udp_user_description(user_port.dw), converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
eth_udp_user_description(8)) eth_udp_user_description(8))
self.submodules += converter self.submodules += converter
self.comb += [ self.comb += [
user_port.sink.connect(converter.sink), user_port.sink.connect(converter.sink),
converter.source.connect(internal_port.sink) converter.source.connect(internal_port.sink)
] ]
converter = stream.Converter(eth_udp_user_description(8), converter = stream.StrideConverter(eth_udp_user_description(8),
eth_udp_user_description(user_port.dw)) eth_udp_user_description(user_port.dw))
self.submodules += converter self.submodules += converter
self.comb += [ self.comb += [
internal_port.source.connect(converter.sink), internal_port.source.connect(converter.sink),

8
liteeth/phy/mii.py
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@ -18,8 +18,8 @@ class LiteEthPHYMIITX(Module):
if hasattr(pads, "tx_er"): if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0) self.sync += pads.tx_er.eq(0)
converter = stream.Converter(converter_description(8), converter = stream.StrideConverter(converter_description(8),
converter_description(4)) converter_description(4))
self.submodules += converter self.submodules += converter
self.comb += [ self.comb += [
converter.sink.stb.eq(sink.stb), converter.sink.stb.eq(sink.stb),
@ -39,8 +39,8 @@ class LiteEthPHYMIIRX(Module):
# # # # # #
converter = stream.Converter(converter_description(4), converter = stream.StrideConverter(converter_description(4),
converter_description(8)) converter_description(8))
converter = ResetInserter()(converter) converter = ResetInserter()(converter)
self.submodules += converter self.submodules += converter

8
liteeth/phy/rmii.py
View File

@ -19,8 +19,8 @@ class LiteEthPHYRMIITX(Module):
# # # # # #
converter = stream.Converter(converter_description(8), converter = stream.StrideConverter(converter_description(8),
converter_description(2)) converter_description(2))
self.submodules += converter self.submodules += converter
self.comb += [ self.comb += [
converter.sink.stb.eq(sink.stb), converter.sink.stb.eq(sink.stb),
@ -40,8 +40,8 @@ class LiteEthPHYRMIIRX(Module):
# # # # # #
converter = stream.Converter(converter_description(2), converter = stream.StrideConverter(converter_description(2),
converter_description(8)) converter_description(8))
converter = ResetInserter()(converter) converter = ResetInserter()(converter)
self.submodules += converter self.submodules += converter