global: use new StrideConverter
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51f56e79dd
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@ -67,12 +67,12 @@ class LiteEthMACCore(Module, AutoCSR):
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# Converters
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if dw != phy.dw:
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reverse = endianness == "big"
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tx_converter = stream.Converter(eth_phy_description(dw),
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eth_phy_description(phy.dw),
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reverse=reverse)
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rx_converter = stream.Converter(eth_phy_description(phy.dw),
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eth_phy_description(dw),
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reverse=reverse)
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tx_converter = stream.StrideConverter(eth_phy_description(dw),
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eth_phy_description(phy.dw),
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reverse=reverse)
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rx_converter = stream.StrideConverter(eth_phy_description(phy.dw),
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eth_phy_description(dw),
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reverse=reverse)
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
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@ -35,15 +35,15 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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user_port = LiteEthUDPUserPort(dw)
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internal_port = LiteEthUDPUserPort(8)
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if dw != 8:
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converter = stream.Converter(eth_udp_user_description(user_port.dw),
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eth_udp_user_description(8))
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converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
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eth_udp_user_description(8))
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self.submodules += converter
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self.comb += [
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user_port.sink.connect(converter.sink),
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converter.source.connect(internal_port.sink)
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]
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converter = stream.Converter(eth_udp_user_description(8),
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eth_udp_user_description(user_port.dw))
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converter = stream.StrideConverter(eth_udp_user_description(8),
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eth_udp_user_description(user_port.dw))
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self.submodules += converter
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self.comb += [
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internal_port.source.connect(converter.sink),
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@ -18,8 +18,8 @@ class LiteEthPHYMIITX(Module):
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if hasattr(pads, "tx_er"):
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self.sync += pads.tx_er.eq(0)
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converter = stream.Converter(converter_description(8),
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converter_description(4))
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converter = stream.StrideConverter(converter_description(8),
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converter_description(4))
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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@ -39,8 +39,8 @@ class LiteEthPHYMIIRX(Module):
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# # #
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converter = stream.Converter(converter_description(4),
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converter_description(8))
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converter = stream.StrideConverter(converter_description(4),
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converter_description(8))
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converter = ResetInserter()(converter)
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self.submodules += converter
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@ -19,8 +19,8 @@ class LiteEthPHYRMIITX(Module):
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# # #
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converter = stream.Converter(converter_description(8),
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converter_description(2))
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converter = stream.StrideConverter(converter_description(8),
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converter_description(2))
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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@ -40,8 +40,8 @@ class LiteEthPHYRMIIRX(Module):
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# # #
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converter = stream.Converter(converter_description(2),
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converter_description(8))
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converter = stream.StrideConverter(converter_description(2),
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converter_description(8))
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converter = ResetInserter()(converter)
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self.submodules += converter
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