phy: add tx/rx_clk_freq to phys (useful to add an add_ethernet method in LiteX and simplify timing constraints).

liteeth/phy/a7_1000basex.py

@@ -41,7 +41,9 @@ class Gearbox(Module):
 
 
 class A7_1000BASEX(Module):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, qpll_channel, data_pads, sys_clk_freq):
         pcs = PCS(lsb_first=True)
         self.submodules += pcs

liteeth/phy/ecp5rgmii.py

@@ -176,7 +176,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRGMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/gmii.py

@@ -83,7 +83,9 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYGMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))

liteeth/phy/gmii_mii.py

@@ -170,7 +170,9 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
 
 
 class LiteEthPHYGMIIMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
         # Note: we can use GMII CRG since it also handles tx clock pad used for MII
         self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)

liteeth/phy/k7_1000basex.py

@@ -42,7 +42,9 @@ class Gearbox(Module):
 
 # Configured for 200MHz transceiver reference clock
 class K7_1000BASEX(Module):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq):
         pcs = PCS(lsb_first=True)
         self.submodules += pcs

liteeth/phy/ku_1000basex.py

@@ -41,7 +41,9 @@ class Gearbox(Module):
 
 # Configured for 200MHz transceiver reference clock
 class KU_1000BASEX(Module):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq):
         pcs = PCS(lsb_first=True)
         self.submodules += pcs

liteeth/phy/mii.py

@@ -90,7 +90,9 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 25e6
+    rx_clk_freq = 25e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))

liteeth/phy/rmii.py

@@ -118,7 +118,9 @@ class LiteEthPHYRMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 50e6
+    rx_clk_freq = 50e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))

liteeth/phy/s6rgmii.py

@@ -258,7 +258,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRGMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/s7rgmii.py

@@ -202,7 +202,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRGMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))

liteeth/phy/usrgmii.py

@@ -212,7 +212,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 
 
 class LiteEthPHYRGMII(Module, AutoCSR):
-    dw = 8
+    dw          = 8
+    tx_clk_freq = 125e6
+    rx_clk_freq = 125e6
     def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
         self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
         self.submodules.tx  = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))