core/udp: Revert TX/RX Buffer since not helping (at least for now).

This commit is contained in:
Florent Kermarrec 2024-04-04 17:52:43 +02:00
parent 211cdc26f3
commit b5d7ba1220
2 changed files with 2 additions and 14 deletions

View File

@ -38,7 +38,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
self.dw = dw
LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port", dw=dw)
def get_port(self, udp_port, dw=8, cd="sys", tx_buffer=False, rx_buffer=False):
def get_port(self, udp_port, dw=8, cd="sys"):
if udp_port in self.users.keys():
raise ValueError("Port {0:#x} already assigned".format(udp_port))
@ -48,12 +48,6 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# TX
# ---
# Buffer.
if tx_buffer:
self.tx_buffer = tx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
self.comb += tx_buffer.source.connect(user_port.sink)
user_port.sink = tx_buffer.sink
# CDC.
self.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
layout = eth_udp_user_description(user_port.dw),
@ -92,12 +86,6 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
# Interface.
self.comb += rx_cdc.source.connect(user_port.source)
# Buffer.
if rx_buffer:
self.rx_buffer = rx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
self.comb += user_port.source.connect(rx_buffer.sink)
user_port.source = rx_buffer.sink
# Expose/Return User Port.
# ------------------------
self.users[udp_port] = internal_port

View File

@ -125,7 +125,7 @@ class LiteEthEtherbonePacket(LiteXModule):
def __init__(self, udp, udp_port, cd="sys"):
self.tx = tx = LiteEthEtherbonePacketTX(udp_port)
self.rx = rx = LiteEthEtherbonePacketRX()
udp_port = udp.crossbar.get_port(udp_port, dw=32, cd=cd, tx_buffer=True, rx_buffer=True)
udp_port = udp.crossbar.get_port(udp_port, dw=32, cd=cd)
self.comb += [
tx.source.connect(udp_port.sink),
udp_port.source.connect(rx.sink)