core/udp: Revert TX/RX Buffer since not helping (at least for now).
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@ -38,7 +38,7 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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self.dw = dw
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LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port", dw=dw)
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def get_port(self, udp_port, dw=8, cd="sys", tx_buffer=False, rx_buffer=False):
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def get_port(self, udp_port, dw=8, cd="sys"):
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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@ -48,12 +48,6 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# TX
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# ---
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# Buffer.
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if tx_buffer:
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self.tx_buffer = tx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
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self.comb += tx_buffer.source.connect(user_port.sink)
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user_port.sink = tx_buffer.sink
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# CDC.
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self.tx_cdc = tx_cdc = stream.ClockDomainCrossing(
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layout = eth_udp_user_description(user_port.dw),
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@ -92,12 +86,6 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# Interface.
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self.comb += rx_cdc.source.connect(user_port.source)
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# Buffer.
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if rx_buffer:
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self.rx_buffer = rx_buffer = stream.Buffer(eth_udp_user_description(user_port.dw))
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self.comb += user_port.source.connect(rx_buffer.sink)
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user_port.source = rx_buffer.sink
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# Expose/Return User Port.
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# ------------------------
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self.users[udp_port] = internal_port
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@ -125,7 +125,7 @@ class LiteEthEtherbonePacket(LiteXModule):
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def __init__(self, udp, udp_port, cd="sys"):
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self.tx = tx = LiteEthEtherbonePacketTX(udp_port)
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self.rx = rx = LiteEthEtherbonePacketRX()
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udp_port = udp.crossbar.get_port(udp_port, dw=32, cd=cd, tx_buffer=True, rx_buffer=True)
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udp_port = udp.crossbar.get_port(udp_port, dw=32, cd=cd)
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self.comb += [
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tx.source.connect(udp_port.sink),
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udp_port.source.connect(rx.sink)
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