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liteeth/core: Allow configuration of full_mem_we parameter

This commit is contained in:
David Sawatzke 2021-08-08 22:25:21 +02:00
parent e14c90dbc3
commit c3b9850366
1 changed files with 7 additions and 6 deletions
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13
liteeth/gen.py
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@ -219,12 +219,13 @@ class MACCore(PHYCore):
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"],
nrxslots = nrxslots,
ntxslots = ntxslots)
phy = self.ethphy,
dw = 32,
interface = "wishbone",
endianness = core_config["endianness"],
nrxslots = nrxslots,
ntxslots = ntxslots,
full_memory_we = core_config.get("full_memory_we", False))
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
self.add_csr("ethmac")