Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteeth/core: Allow configuration of full_mem_we parameter

This commit is contained in:
David Sawatzke 2021-08-08 22:25:21 +02:00
parent e14c90dbc3
commit c3b9850366
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
liteeth/gen.py
View File

@ -219,12 +219,13 @@ class MACCore(PHYCore):
# MAC -------------------------------------------------------------------------------------- # MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC( self.submodules.ethmac = LiteEthMAC(
phy = self.ethphy, phy = self.ethphy,
dw = 32, dw = 32,
interface = "wishbone", interface = "wishbone",
endianness = core_config["endianness"], endianness = core_config["endianness"],
nrxslots = nrxslots, nrxslots = nrxslots,
ntxslots = ntxslots) ntxslots = ntxslots,
full_memory_we = core_config.get("full_memory_we", False))
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io") self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
self.add_csr("ethmac") self.add_csr("ethmac")