liteeth/core: Allow configuration of full_mem_we parameter

2021-08-08 22:25:21 +02:00 · 2021-08-08 22:25:21 +02:00 · c3b9850366
parent e14c90dbc3
commit c3b9850366
1 changed files with 7 additions and 6 deletions
--- a/liteeth/gen.py
+++ b/liteeth/gen.py
@ -224,7 +224,8 @@ class MACCore(PHYCore):
            interface      = "wishbone",
            endianness     = core_config["endianness"],
            nrxslots       = nrxslots,
-            ntxslots   = ntxslots)
+            ntxslots       = ntxslots,
+            full_memory_we = core_config.get("full_memory_we", False))
        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
        self.add_memory_region("ethmac", self.mem_map["ethmac"], mac_memsize, type="io")
        self.add_csr("ethmac")