bench/targets: add identifier and SRAM.

This commit is contained in:
Florent Kermarrec 2020-11-23 17:11:36 +01:00
parent 291b257eb4
commit c7d7561a38
2 changed files with 14 additions and 2 deletions

View File

@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
platform = arty.Platform()
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteEth bench on Arty",
ident_version = True
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# SRAM -------------------------------------------------------------------------------------
self.add_ram("sram", 0x20000000, 0x1000)
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(

View File

@ -28,7 +28,10 @@ class BenchSoC(SoCCore):
platform = genesys2.Platform()
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, uart_name="bridge")
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteEth bench on Genesys2",
ident_version = True
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -41,6 +44,9 @@ class BenchSoC(SoCCore):
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# SRAM -------------------------------------------------------------------------------------
self.add_ram("sram", 0x20000000, 0x1000)
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(