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core/mac: pass endianness and use if for last_be gen/check

This commit is contained in:
Florent Kermarrec 2018-09-07 10:35:27 +02:00
parent 94af3d63d9
commit ce72e34f56
3 changed files with 36 additions and 33 deletions
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2
liteeth/core/mac/__init__.py
View File

@ -27,7 +27,7 @@ class LiteEthMAC(Module, AutoCSR):
self.rx_slots = CSRConstant(nrxslots) self.rx_slots = CSRConstant(nrxslots)
self.tx_slots = CSRConstant(ntxslots) self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu)) self.slot_size = CSRConstant(2**bits_for(eth_mtu))
self.submodules.interface = LiteEthMACWishboneInterface(dw, nrxslots, ntxslots) self.submodules.interface = LiteEthMACWishboneInterface(dw, nrxslots, ntxslots, endianness)
self.comb += Port.connect(self.interface, self.core) self.comb += Port.connect(self.interface, self.core)
self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() + self.core.get_csrs() self.csrs = self.interface.get_csrs() + self.core.get_csrs()

63
liteeth/core/mac/sram.py
View File

@ -5,7 +5,7 @@ from litex.soc.interconnect.csr_eventmanager import *
class LiteEthMACSRAMWriter(Module, AutoCSR): class LiteEthMACSRAMWriter(Module, AutoCSR):
def __init__(self, dw, depth, nslots=2): def __init__(self, dw, depth, nslots=2, endianness="big"):
self.sink = sink = stream.Endpoint(eth_phy_description(dw)) self.sink = sink = stream.Endpoint(eth_phy_description(dw))
self.crc_error = Signal() self.crc_error = Signal()
@ -27,17 +27,19 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
sink.ready.reset = 1 sink.ready.reset = 1
# length computation # length computation
increment = Signal(3) inc = Signal(3)
self.comb += \ inc_cases = {}
If(sink.last_be[3], inc_cases["default"] = inc.eq(4)
increment.eq(1) if endianness == "big":
).Elif(sink.last_be[2], inc_cases[0b1000] = inc.eq(1)
increment.eq(2) inc_cases[0b0100] = inc.eq(2)
).Elif(sink.last_be[1], inc_cases[0b0010] = inc.eq(3)
increment.eq(3) else:
).Else( inc_cases[0b0001] = inc.eq(1)
increment.eq(4) inc_cases[0b0010] = inc.eq(2)
) inc_cases[0b0100] = inc.eq(3)
self.comb += Case(sink.last_be, inc_cases)
counter = Signal(lengthbits) counter = Signal(lengthbits)
counter_reset = Signal() counter_reset = Signal()
counter_ce = Signal() counter_ce = Signal()
@ -45,7 +47,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
If(counter_reset, If(counter_reset,
counter.eq(0) counter.eq(0)
).Elif(counter_ce, ).Elif(counter_ce,
counter.eq(counter + increment) counter.eq(counter + inc)
) )
# slot computation # slot computation
@ -140,7 +142,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
class LiteEthMACSRAMReader(Module, AutoCSR): class LiteEthMACSRAMReader(Module, AutoCSR):
def __init__(self, dw, depth, nslots=2): def __init__(self, dw, depth, nslots=2, endianness="big"):
self.source = source = stream.Endpoint(eth_phy_description(dw)) self.source = source = stream.Endpoint(eth_phy_description(dw))
slotbits = max(log2_int(nslots), 1) slotbits = max(log2_int(nslots), 1)
@ -202,20 +204,21 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
NextState("END"), NextState("END"),
) )
) )
length_lsb = fifo.source.length[0:2] length_lsb = fifo.source.length[0:2]
self.comb += [ length_cases = {}
If(last, if endianness == "big":
If(length_lsb == 3, length_cases[0] = source.last_be.eq(0b0001)
source.last_be.eq(0b0010) length_cases[1] = source.last_be.eq(0b1000)
).Elif(length_lsb == 2, length_cases[2] = source.last_be.eq(0b0100)
source.last_be.eq(0b0100) length_cases[3] = source.last_be.eq(0b0010)
).Elif(length_lsb == 1, else:
source.last_be.eq(0b1000) length_cases[0] = source.last_be.eq(0b1000)
).Else( length_cases[1] = source.last_be.eq(0b0001)
source.last_be.eq(0b0001) length_cases[2] = source.last_be.eq(0b0010)
) length_cases[3] = source.last_be.eq(0b0100)
) self.comb += If(last, Case(length_lsb, length_cases))
]
fsm.act("SEND", fsm.act("SEND",
source.valid.eq(1), source.valid.eq(1),
source.last.eq(last), source.last.eq(last),
@ -253,8 +256,8 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
class LiteEthMACSRAM(Module, AutoCSR): class LiteEthMACSRAM(Module, AutoCSR):
def __init__(self, dw, depth, nrxslots, ntxslots): def __init__(self, dw, depth, nrxslots, ntxslots, endianness):
self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots) self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness)
self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots) self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots, endianness)
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev) self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
self.sink, self.source = self.writer.sink, self.reader.source self.sink, self.source = self.writer.sink, self.reader.source

4
liteeth/core/mac/wishbone.py
View File

@ -7,7 +7,7 @@ from litex.soc.interconnect import wishbone
class LiteEthMACWishboneInterface(Module, AutoCSR): class LiteEthMACWishboneInterface(Module, AutoCSR):
def __init__(self, dw, nrxslots=2, ntxslots=2): def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big"):
self.sink = stream.Endpoint(eth_phy_description(dw)) self.sink = stream.Endpoint(eth_phy_description(dw))
self.source = stream.Endpoint(eth_phy_description(dw)) self.source = stream.Endpoint(eth_phy_description(dw))
self.bus = wishbone.Interface() self.bus = wishbone.Interface()
@ -16,7 +16,7 @@ class LiteEthMACWishboneInterface(Module, AutoCSR):
# storage in SRAM # storage in SRAM
sram_depth = eth_mtu//(dw//8) sram_depth = eth_mtu//(dw//8)
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness)
self.comb += [ self.comb += [
self.sink.connect(self.sram.sink), self.sink.connect(self.sram.sink),
self.sram.source.connect(self.source) self.sram.source.connect(self.source)