global: Switch to litex.gen.genlib.misc.

This commit is contained in:
Florent Kermarrec 2023-07-06 22:06:37 +02:00
parent 4954026a26
commit e5168fe142
6 changed files with 6 additions and 6 deletions

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@ -11,9 +11,9 @@ import argparse
from migen import *
from migen.genlib.cdc import MultiReg
from migen.genlib.misc import WaitTimer
from litex.gen import *
from litex.gen.genlib.misc import WaitTimer
from litex_boards.platforms import digilent_arty
from litex_boards.targets.digilent_arty import _CRG

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@ -6,7 +6,7 @@
from liteeth.common import *
from migen.genlib.misc import WaitTimer
from litex.gen.genlib.misc import WaitTimer
from liteeth.packet import Depacketizer, Packetizer

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@ -19,9 +19,9 @@ issue a DHCP request regularly. Limitations is due to 32-bit data-path and parsi
"""
from migen import *
from migen.genlib.misc import WaitTimer
from litex.gen import *
from litex.gen.genlib.misc import WaitTimer
from liteeth.common import *

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@ -15,7 +15,7 @@ from math import ceil
from liteeth.common import *
from migen.genlib.misc import chooser, WaitTimer
from litex.gen.genlib.misc import chooser, WaitTimer
# MAC CRC Engine -----------------------------------------------------------------------------------

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@ -9,7 +9,7 @@
from liteeth.common import *
from migen.genlib.misc import chooser
from litex.gen.genlib.misc import chooser
# MAC Preamble Inserter ----------------------------------------------------------------------------

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@ -8,10 +8,10 @@ from math import ceil
from migen import *
from migen.genlib.fsm import *
from migen.genlib.misc import WaitTimer
from migen.genlib.cdc import PulseSynchronizer, BusSynchronizer
from litex.gen import *
from litex.gen.genlib.misc import WaitTimer
from litex.soc.interconnect import stream
from litex.soc.cores.code_8b10b import K, D, Encoder, Decoder