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phy/pcs_1000basex: Add missing RX Align during AUTONEG_WAIT_ABI state and enable/connect it on all PHYs.

This commit is contained in:
Florent Kermarrec 2024-10-15 09:47:46 +02:00
parent 7e602c406d
commit e5746c8a81
7 changed files with 21 additions and 18 deletions
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6
liteeth/phy/a7_1000basex.py
View File

@ -505,9 +505,9 @@ class A7_1000BASEX(LiteXModule):
o_RXBYTEISALIGNED = Open(),
o_RXBYTEREALIGN = Open(),
o_RXCOMMADET = Open(),
i_RXCOMMADETEN = 0,
i_RXMCOMMAALIGNEN = 0,
i_RXPCOMMAALIGNEN = 0,
i_RXCOMMADETEN = 0b1,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXPCOMMAALIGNEN = pcs.align,
i_RXSLIDE = 0,
# Receive Ports - RX Channel Bonding Ports
o_RXCHANBONDSEQ = Open(),

6
liteeth/phy/k7_1000basex.py
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@ -484,9 +484,9 @@ class K7_1000BASEX(LiteXModule):
o_RXBYTEISALIGNED = Open(),
o_RXBYTEREALIGN = Open(),
o_RXCOMMADET = Open(),
i_RXCOMMADETEN = 1,
i_RXMCOMMAALIGNEN = 1,
i_RXPCOMMAALIGNEN = 1,
i_RXCOMMADETEN = 0b1,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXPCOMMAALIGNEN = pcs.align,
# Receive Ports - RX Channel Bonding Ports
o_RXCHANBONDSEQ = Open(),

6
liteeth/phy/ku_1000basex.py
View File

@ -536,7 +536,7 @@ class KU_1000BASEX(LiteXModule):
i_RXCHBONDLEVEL = 0b000,
i_RXCHBONDMASTER = 0b0,
i_RXCHBONDSLAVE = 0b0,
i_RXCOMMADETEN = 0b0,
i_RXCOMMADETEN = 0b1,
i_RXDFEAGCCTRL = 0b01,
i_RXDFEAGCHOLD = 0b0,
i_RXDFEAGCOVRDEN = 0b0,
@ -593,7 +593,7 @@ class KU_1000BASEX(LiteXModule):
i_RXLPMLFKLOVRDEN = 0b0,
i_RXLPMOSHOLD = 0b0,
i_RXLPMOSOVRDEN = 0b0,
i_RXMCOMMAALIGNEN = 0b0,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXMONITORSEL = 0b00,
i_RXOOBRESET = 0b0,
i_RXOSCALRESET = 0b0,
@ -606,7 +606,7 @@ class KU_1000BASEX(LiteXModule):
i_RXOSINTTESTOVRDEN = 0b0,
i_RXOSOVRDEN = 0b0,
i_RXOUTCLKSEL = 0b101,
i_RXPCOMMAALIGNEN = 0b0,
i_RXPCOMMAALIGNEN = pcs.align,
i_RXPCSRESET = 0b0,
i_RXPD = 0b00,
i_RXPHALIGNEN = 0b0,

3
liteeth/phy/pcs_1000basex.py
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@ -297,6 +297,8 @@ class PCS(LiteXModule):
self.link_up = Signal()
self.restart = Signal()
self.align = Signal()
self.lp_abi = BusSynchronizer(16, "eth_rx", "eth_tx")
@ -387,6 +389,7 @@ class PCS(LiteXModule):
)
# ABILITY_DETECT
fsm.act("AUTONEG_WAIT_ABI",
self.align.eq(1),
self.tx.config_valid.eq(1),
If(rx_config_reg_abi.o,
NextState("AUTONEG_WAIT_ACK")

6
liteeth/phy/usp_gth_1000basex.py
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@ -612,7 +612,7 @@ class USP_GTH_1000BASEX(LiteXModule):
i_RXCHBONDLEVEL = 0b000,
i_RXCHBONDMASTER = 0b0,
i_RXCHBONDSLAVE = 0b0,
i_RXCOMMADETEN = 0b0,
i_RXCOMMADETEN = 0b1,
i_RXDFEAGCCTRL = 0b01,
i_RXDFEAGCHOLD = 0b0,
i_RXDFEAGCOVRDEN = 0b0,
@ -668,14 +668,14 @@ class USP_GTH_1000BASEX(LiteXModule):
i_RXLPMLFKLOVRDEN = 0b0,
i_RXLPMOSHOLD = 0b0,
i_RXLPMOSOVRDEN = 0b0,
i_RXMCOMMAALIGNEN = 0b0,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXMONITORSEL = 0b00,
i_RXOOBRESET = 0b0,
i_RXOSCALRESET = 0b0,
i_RXOSHOLD = 0b0,
i_RXOSOVRDEN = 0b0,
i_RXOUTCLKSEL = 0b101,
i_RXPCOMMAALIGNEN = 0b0,
i_RXPCOMMAALIGNEN = pcs.align,
i_RXPCSRESET = 0b0,
i_RXPD = 0b00,
i_RXPHALIGNEN = 0b0,

6
liteeth/phy/usp_gty_1000basex.py
View File

@ -641,7 +641,7 @@ class USP_GTY_1000BASEX(LiteXModule):
i_RXCHBONDSLAVE = 0b0,
i_RXCKCALRESET = 0b0,
i_RXCKCALSTART = 0b0,
i_RXCOMMADETEN = 0b0,
i_RXCOMMADETEN = 0b1,
i_RXDFEAGCHOLD = 0b0,
i_RXDFEAGCOVRDEN = 0b0,
i_RXDFECFOKFCNUM = 0b0,
@ -704,14 +704,14 @@ class USP_GTY_1000BASEX(LiteXModule):
i_RXLPMLFKLOVRDEN = 0b0,
i_RXLPMOSHOLD = 0b0,
i_RXLPMOSOVRDEN = 0b0,
i_RXMCOMMAALIGNEN = 0b0,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXMONITORSEL = 0b00,
i_RXOOBRESET = 0b0,
i_RXOSCALRESET = 0b0,
i_RXOSHOLD = 0b0,
i_RXOSOVRDEN = 0b0,
i_RXOUTCLKSEL = 0b101,
i_RXPCOMMAALIGNEN = 0b0,
i_RXPCOMMAALIGNEN = pcs.align,
i_RXPCSRESET = 0b0,
i_RXPD = 0b00,
i_RXPHALIGN = 0b0,

6
liteeth/phy/v7_1000basex.py
View File

@ -479,9 +479,9 @@ class V7_1000BASEX(LiteXModule):
o_RXBYTEISALIGNED = Open(),
o_RXBYTEREALIGN = Open(),
o_RXCOMMADET = Open(),
i_RXCOMMADETEN = 1,
i_RXMCOMMAALIGNEN = 1,
i_RXPCOMMAALIGNEN = 1,
i_RXCOMMADETEN = 0b1,
i_RXMCOMMAALIGNEN = pcs.align,
i_RXPCOMMAALIGNEN = pcs.align,
# Receive Ports - RX Channel Bonding Ports
o_RXCHANBONDSEQ = Open(),