phy/xgmii: handle IFG insertion in PHY, support deficit idle count
Because XGMII only allows start of frame characters to be placed on lane 0 (first octet in a 32-bit XGMII bus word), when a packet's length % 4 != 0, we can't transmit exactly 12 XGMII idle characters inter-frame gap (the XGMII end of frame character counts towards the inter-frame gap, while start of frame does not). Given we are required to transmit a minimum of 12 bytes IFG, it's allowed to send packet length % 4 bytes additional IFG bytes. However this would waste precious bandwidth transmitting these characters. Thus, 10Gbit/s Ethernet and above allow using the deficit idle count mechanism. It allows to delete some idle characters, as long as an average count of >= 12 bytes IFG is maintained. This is to be implemented as a two bit counter as specified in IEEE802.3-2018, section four, 46.3.1.4 Start control character alignment. In practice, the previous implementation of the LiteEthPHYXGMIITX made these issues even more prevalent: because the internal stream interface is 64-bit wide and stream transactions always start aligned to the first octet in a bus word, the previous primitive TX implementation always started transmission on the first octet in the 64-bit XGMII bus word. The IFG inserter operated independently if the PHY and thus made sure to maintain 12 bytes of IFG on the 64-bit stream bus. This means that in a worst case scenario, the IFG could grow to 23 octets. In applications such as Ethernet switches, the consequences would be frequent buffer overruns or corrupt transmissions. Hence this commit introduces a IFG inserter in the LiteEthPHYXGMIITX module itself. It is significantly more complex compared to the gap inserter, but inserts the smallest legal gap as defined by IEEE802.3. Furthermore, it optionally implements the deficit idle count algorithm as described by Eric Lynskey of the UNH InterOperability Lab1 to achieve an average IFG of 12 bytes. Signed-off-by: Leon Schuermann <leon@is.currently.online>
This commit is contained in:
Leon Schuermann
parent
1bbd90ae4d
commit
ea0a65d357
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@ -125,7 +125,8 @@ class LiteEthMACCore(Module, AutoCSR):
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if core_dw != 8:
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tx_datapath.add_last_be()
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# Gap insertion has to occurr in phy tx domain to ensure gap is correctly maintained
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tx_datapath.add_gap()
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if not getattr(phy, "integrated_ifg_inserter", False):
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tx_datapath.add_gap()
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tx_datapath.pipeline.append(phy)
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self.submodules.tx_datapath = tx_datapath
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@ -17,66 +17,382 @@ XGMII_START = Constant(0xFB, bits_sign=8)
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XGMII_END = Constant(0xFD, bits_sign=8)
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class LiteEthPHYXGMIITX(Module):
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def __init__(self, pads, dw):
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def __init__(self, pads, dw, dic=True):
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# Enforce 64-bit data path
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assert dw == 64
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# Sink for data to transmit
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self.sink = sink = stream.Endpoint(eth_phy_description(dw))
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# ---------- Generic signals ----------
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# Masked last_be signal of current clock cycle. last_be should only be
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# respected when last is also asserted.
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masked_last_be = Signal.like(sink.last_be)
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self.comb += [
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If(sink.last,
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masked_last_be.eq(sink.last_be),
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),
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]
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# ---------- Inter-frame gap state ----------
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# State to keep track of the current inter-frame gap we are required to
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# maintain. We must take care to always have an inter-frame gap of at
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# least 96 bits (12 bytes), with an exception for the deficit idle gap
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# mechanism. Because XGMII transactions can only start on the first or
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# fifth byte in a 64-bit bus word, it's sufficient to represent this as
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# - 0: less than 4 bytes of IFG transmitted
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# - 1: less than 8 bytes of IFG transmitted
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# - 2: less than 12 bytes of IFG transmitted
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# - 3: 12 or more bytes of IFG transmitted
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current_ifg = Signal(max=4, reset=3)
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next_ifg = Signal(max=4)
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# Shortcut "functions" to add a 32-bit or 64-bit idle bus word to the
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# current inter-frame gap without worring about wrapping, or to reset it
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# (typically on the start of a new transmission). This can be useful to
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# see the effect on the next_ifg value and thus make decisions about
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# subsequent signal states (e.g. sink.ready).
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ifg_reset = Signal()
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ifg_add_double = Signal()
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ifg_add_single = Signal()
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self.comb += [
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If(ifg_reset,
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next_ifg.eq(0),
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).Elif(ifg_add_single,
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If(current_ifg < 3,
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next_ifg.eq(current_ifg + 1)
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),
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).Elif(ifg_add_double,
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If(current_ifg < 2,
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next_ifg.eq(current_ifg + 2),
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).Else(
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next_ifg.eq(3),
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),
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).Else(
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next_ifg.eq(current_ifg),
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),
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]
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self.sync += current_ifg.eq(next_ifg)
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# ---------- Deficit idle count mechanism state ----------
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# Because XGMII only allows start of frame characters to be placed on
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# lane 0 (first and fifth octet in a 64-bit bus word), when a packet's
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# length % 4 != 0, we can't transmit exactly 12 XGMII idle characters
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# inter-frame gap (the XGMII end of frame character counts towards the
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# inter-frame gap, while start of frame does not). Given we are required
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# to transmit a minimum of 12 bytes IFG, it's allowed to send packet
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# length % 4 bytes additional IFG bytes. However this would waste
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# precious bandwidth transmitting these characters.
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#
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# Thus, 10Gbit/s Ethernet and above allow using the deficit idle count
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# mechanism. It allows to delete some idle characters, as long as an
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# average count of >= 12 bytes IFG is maintained. This is to be
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# implemented as a two bit counter as specified in IEEE802.3-2018,
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# section four, 46.3.1.4 Start control character alignment.
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#
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# This module implements the deficit idle count algorithm as described
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# by Eric Lynskey of the UNH InterOperability Lab[1]:
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#
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# | current | | | | |
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# | count | 0 | 1 | 2 | 3 |
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# |---------+-----+-------+-----+-------+-----+-------+-----+-------|
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# | | | new | | new | | new | | new |
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# | pkt % 4 | IFG | count | IFG | count | IFG | count | IFG | count |
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# |---------+-----+-------+-----+-------+-----+-------+-----+-------|
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# | 0 | 12 | 0 | 12 | 1 | 12 | 2 | 12 | 3 |
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# | 1 | 11 | 1 | 11 | 2 | 11 | 3 | 15 | 0 |
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# | 2 | 10 | 2 | 10 | 3 | 14 | 0 | 14 | 1 |
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# | 3 | 9 | 3 | 13 | 0 | 13 | 1 | 13 | 2 |
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#
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# [1]: https://www.iol.unh.edu/sites/default/files/knowledgebase/10gec/10GbE_DIC.pdf
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# Additional state to keep track of exactly how many bytes % 4 we've
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# transmitted in the last packet. We need this information to judge
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# whether we've had a sufficiently large IFG given the current DIC
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# count. Value the range of [0; 3].
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#
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# If we disable the deficit idle count, we replace this with a constant
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# of 0, meaning that we pretend to not have transmitted any additional
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# IDLE characters. This should allow significant logic optimizations
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# while having the same effect as not implementing DIC at all.
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if dic:
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last_packet_rem = Signal(max=4)
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else:
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last_packet_rem = Constant(0, bits_sign=2)
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# Bounded counter of deleted XGMII idle characters. Must be within [0;
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# 3]. If we disable the deficit idle count mechanism, this signal should
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# not change. However, it's still present to avoid the logic below
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# getting too complex.
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current_dic = Signal(max=4, reset=3)
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# ---------- Shifted transmit state ----------
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# Whether the current transmission is shifted, meaning that the packet's
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# transmission started on the fifth octect within the 64-bit bus
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# word. As a consequence of the shifted transmission, given that we
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# receive 64 valid bits from the sink, we need to store and delay the
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# upper half of the current clock cycle's data to the next.
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#
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# This register is to be set when transitioning out of the IDLE
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# state.
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transmit_shifted = Signal()
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# Upper half of the data of the previous clock cycle.
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prev_valid_data = Signal(dw)
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prev_valid_last_be = Signal(dw // 8)
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self.sync += [
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If(sink.valid & sink.ready,
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prev_valid_data.eq(sink.data),
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If(sink.last,
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prev_valid_last_be.eq(masked_last_be)
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).Else(
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prev_valid_last_be.eq(0),
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),
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),
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]
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# Previous clock cycle sink valid signal
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prev_valid = Signal()
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self.sync += prev_valid.eq(sink.valid)
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# Adjusted sink data & last_be. If our transmission is shifted, this
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# will contain the upper-half of the previous and lower-half of the
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# current clock cycle. Otherwise, simply equal to data and the masked
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# last_be.
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adjusted_sink_valid = Signal()
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adjusted_sink_valid_data = Signal.like(sink.data)
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adjusted_sink_valid_last_be = Signal.like(sink.last_be)
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self.comb += [
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If(transmit_shifted,
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# Because we are injecting data from the previous cycle, we need
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# to respect it's valid. It's fine that adjusted_sink_valid
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# therefore is deasserted for the very first bus word, given
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# this is handled in the IDLE fsm state still. This assumes a
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# non-hostile sink where valid is constantly asserted during a
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# single transmission.
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adjusted_sink_valid.eq(prev_valid),
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adjusted_sink_valid_data.eq(Cat(
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prev_valid_data[(dw // 2):],
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sink.data[:(dw // 2)],
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)),
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adjusted_sink_valid_last_be.eq(Cat(
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prev_valid_last_be[(dw // 8 // 2):],
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masked_last_be[:(dw // 8 // 2)],
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)),
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).Else(
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adjusted_sink_valid.eq(sink.valid),
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adjusted_sink_valid_data.eq(sink.data),
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adjusted_sink_valid_last_be.eq(masked_last_be),
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),
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]
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# ---------- XGMII transmission logic ----------
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# Transmit FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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# This block will be executed by the FSM below in the IDLE state, when
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# it's time to start a transmission aligned on the FIRST byte in a
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# 64-bit bus word. This can happen both because we've waited the 12 byte
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# IFG and coincidentally the first byte is the next valid start point,
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# or because we reduced the IFG to 8 bytes because of the deficit idle
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# count mechanism. Thus have it as a reusable component here.
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unshifted_idle_transmit = [
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# Currently idling, but a new frame is ready for transmission
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# and we had at least the full IFG idle before. Thus transmit
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# the preamble, but replace the first byte with the XGMII start
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# of frame control character. Accept more data.
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ifg_reset.eq(1),
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pads.tx_ctl.eq(0x01),
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pads.tx_data.eq(Cat(XGMII_START, sink.data[8:dw])),
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NextValue(transmit_shifted, 0),
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NextValue(sink.ready, 1),
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NextState("TRANSMIT"),
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]
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# This block will be executed by the FSM below in the IDLE state, when
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# it's time to start a transmission aligned on the FIFTH byte in a
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# 64-bit bus word. This can happen either because we've waited the 8
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# byte IFG and need to insert only four bytes more in this cycle, or
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# because the deficit idle count mechanism allows transmit with a
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# smaller IFG (e.g. 1 bits packet remainder + 4 bytes TRANSMIT IFG in
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# previous cycle + 4 bytes IDLE ID in current cycle = 9 bytes total
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# IFG).
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shifted_idle_transmit = [
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# Currently idling, but a new frame is ready for transmission and
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# there is only 4 bytes missing in the IFG (or we have created an
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# acceptable IFG deficit). Thus transmit the preamble on the second
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# 32-bit bus word, but replace the first byte with the XGMII start
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# of frame control character. Accept more data.
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pads.tx_ctl.eq(0x1F),
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pads.tx_data.eq(Cat(
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Replicate(XGMII_IDLE, 4),
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XGMII_START,
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sink.data[8:(dw // 2)],
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)),
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ifg_reset.eq(1),
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NextValue(transmit_shifted, 1),
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NextValue(sink.ready, 1),
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NextState("TRANSMIT"),
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]
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fsm.act("IDLE",
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If(sink.valid,
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# Currently idling, but a new frame is ready for
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# transmission. Thus transmit the preamble, but replace the
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# first byte with the XGMII start of frame control
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# character. Accept more data.
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pads.tx_ctl.eq(0x01),
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pads.tx_data.eq(Cat(XGMII_START, sink.data[8:dw])),
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NextValue(sink.ready, 1),
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NextState("TRANSMIT"),
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If(sink.valid & (current_ifg == 3),
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# Branch A: we've transmitted at least the full 12 bytes
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# IFG. This means that we can unconditionally start transmission
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# on the first octet. In addition to that, we may have inserted
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# some extra XGMII, thus we can reduce the deficit.
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*unshifted_idle_transmit,
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If(current_dic - last_packet_rem < 0,
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NextValue(current_dic, 0),
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).Else(
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NextValue(current_dic, current_dic - last_packet_rem),
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)
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).Elif(sink.valid & (current_ifg == 2),
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# Branch B: we've transmitted at least 8 bytes of IFG. This
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# means that we can either, depending on the DIC start
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# transmission on the first or fith octect. Manipulate the DIC
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# count accordingly.
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If((last_packet_rem != 0)
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& (current_dic + last_packet_rem <= 3),
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# We've taken some extra IFG bytes (added to the deficit)
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*unshifted_idle_transmit,
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NextValue(current_dic, current_dic + last_packet_rem),
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).Else(
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# We might have inserted some extra IFG bytes (subtracted
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# from the deficit)
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*shifted_idle_transmit,
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If(current_dic - last_packet_rem < 0,
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NextValue(current_dic, 0),
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).Else(
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NextValue(current_dic, current_dic - last_packet_rem),
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)
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),
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).Elif(sink.valid & (current_ifg == 1) & (last_packet_rem != 0)
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& (current_dic + last_packet_rem <= 3),
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# Branch C: we've transmitted at least 4 bytes of IFG. Whether
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# we can start a new transmission here depends on the DIC. In
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# any case, we're deleting at least one XGMII idle character,
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# which we need to keep track of. Furthermore, transmission can
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# only ever start on the fifth octect here.
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*shifted_idle_transmit,
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NextValue(current_dic, current_dic + last_packet_rem),
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).Else(
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# Idling, transmit XGMII IDLE control characters
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# only. Accept more data.
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# Idling, transmit XGMII IDLE control characters only and add
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# them to the IFG.
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pads.tx_ctl.eq(0xFF),
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pads.tx_data.eq(Cat(*([XGMII_IDLE] * 8))),
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NextValue(sink.ready, 1),
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ifg_add_double.eq(1),
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# Accept more data if we've had a sufficiently large inter-frame
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# gap (accounting for deficit idle count). For this we need to
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# determine whether the next sink.valid clock cycle will take a
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# given branch of A, B or C.
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If((next_ifg >= 2)
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| ((next_ifg == 1) & (last_packet_rem != 0)
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& (current_dic + last_packet_rem <= 3)),
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# Branch A, B or C will be taken as soon as sink.valid
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# again, thus accept more data.
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NextValue(sink.ready, 1),
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).Else(
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# We haven't transmitted a sufficient IFG. The next
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# sink.valid clock cycle will not start a transmission.
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NextValue(sink.ready, 0),
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),
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# If we've remained in IDLE because the sink is not yet valid,
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# even though the full IFG has been sent already, remove any
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# deficit idle count. We've made up for that by now.
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If(current_ifg >= 2,
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NextValue(current_dic, 0),
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),
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NextState("IDLE"),
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)
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)
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# How many bytes % 4 we've transmitted in the current packet. This
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# signal is to be asserted when the packet ends in the current clock
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# cycle.
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#
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# If we disable the deficit idle count, we replace this with a constant
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# of 0, meaning that we pretend to not have transmitted any additional
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# IDLE characters. This should allow significant logic optimizations.
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if dic:
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current_packet_rem = Signal(max=4)
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else:
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current_packet_rem = Constant(0, bits_sign=2)
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# Wether the current transmission must be ended in the next clock
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# cycle. This might be required if we haven't transmitted the XGMII end
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# of frame control character, but send all other data of the packet.
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end_transmission = Signal()
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fsm.act("TRANSMIT",
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# Check whether the data is still valid first or we are are not
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# ready to accept a new transmission.
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If(~sink.valid | ~sink.ready,
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# Data isn't valid, or we aren't ready to accept a new
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# transmission yet as another one has ended but the XGMII end of
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# frame control character has not been transmitted. We must
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# transmit the end of frame marker and return to
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# afterwards. Immediately accept more data, given we have
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# transmitted the end of frame control character.
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If(end_transmission | ~adjusted_sink_valid,
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# Data isn't valid, but we're still in the transmit state. This
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# can happen because we've finished transmitting all packet
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# data, but must still transmit the XGMII end of frame control
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# character. Thus put this control character and IDLE on the
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# line, return to IDLE afterwards.
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pads.tx_ctl.eq(0xFF),
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pads.tx_data.eq(Cat(XGMII_END, Replicate(XGMII_IDLE, 7))),
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# Also, we're transmitting 64 bits worth of idle characters.
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ifg_add_double.eq(1),
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# We're transmitting 8 bytes of IFG in this cycle. Thus we know
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# that in the next cycle we can for sure start a new
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# transmission, irrespective of whether we use DIC (either on
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# the first or fifth byte in the 64-bit word). Thus set
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# sink.ready accordingly.
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NextValue(sink.ready, 1),
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# Packet transmission is complete, return to IDLE and reset the
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# end_transmission register.
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NextValue(end_transmission, 0),
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NextState("IDLE"),
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).Else(
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# The data is valid. For each byte, determine whether it is
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# valid or must be an XGMII idle or end of frame control
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# character based on the value of last_be.
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*[
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If(~sink.last | (sink.last_be >= (1 << i)),
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If((adjusted_sink_valid_last_be == 0)
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| (adjusted_sink_valid_last_be >= (1 << i)),
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# Either not the last data word or last_be indicates
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# this byte is still valid
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pads.tx_ctl[i].eq(0),
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pads.tx_data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)]),
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).Elif((sink.last_be == (1 << (i - 1))) if i > 0 else 0,
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pads.tx_data[8*i:8*(i+1)].eq(
|
||||
adjusted_sink_valid_data[8*i:8*(i+1)]
|
||||
),
|
||||
).Elif((adjusted_sink_valid_last_be == (1 << (i - 1)))
|
||||
if i > 0 else 0,
|
||||
# last_be indicates that this byte is the first one
|
||||
# which is no longer valid, hence transmit the XGMII end
|
||||
# of frame character
|
||||
pads.tx_ctl[i].eq(1),
|
||||
pads.tx_data[8*i:8*(i+1)].eq(XGMII_END),
|
||||
# Also, starting from this character, the inter-frame
|
||||
# gap starts. Depending on where we are in the bus word
|
||||
# (index 0 to 4) we can already count cycle as one
|
||||
# 32-bit IFG step (the XGMII end of frame character
|
||||
# counts towards the IFG).
|
||||
If(i < 5,
|
||||
ifg_add_single.eq(1),
|
||||
),
|
||||
# If the DIC mechanism is enabled, furthermore keep
|
||||
# track of the remainder (mod 4) of IDLE bytes being
|
||||
# sent.
|
||||
*([
|
||||
current_packet_rem.eq(i % 4),
|
||||
NextValue(last_packet_rem, i % 4),
|
||||
] if dic else []),
|
||||
).Else(
|
||||
# We must've transmitted the XGMII end of frame control
|
||||
# character, all other bytes must be XGMII idle control
|
||||
|
|
@ -93,15 +409,42 @@ class LiteEthPHYXGMIITX(Module):
|
|||
# XGMII bus word containing the XGMII end of frame and idle
|
||||
# control characters. This happens if we remain in the TRANSMIT
|
||||
# state.
|
||||
If(~sink.last,
|
||||
NextValue(sink.ready, 1),
|
||||
If(adjusted_sink_valid_last_be == 0,
|
||||
# This hasn't been the last bus word. However, before we can
|
||||
# tell the data sink to send us additional data, in case
|
||||
# we're performing a shifted transmission, we must see
|
||||
# whether the current sink data word already indicates the
|
||||
# end of data in it's upper half. If so, we must not request
|
||||
# additional data. Otherwise we could loose valid data, as
|
||||
# we're transmitting the IFG first.
|
||||
If(transmit_shifted & sink.last
|
||||
& ((sink.last_be & 0xF0) != 0),
|
||||
# We're in a shifted transmit and already have received
|
||||
# the last data bytes from the sink.
|
||||
NextValue(sink.ready, 0),
|
||||
).Else(
|
||||
# Everything's good, the sink hasn't yet asserted last.
|
||||
NextValue(sink.ready, 1),
|
||||
),
|
||||
NextState("TRANSMIT"),
|
||||
).Elif(sink.last_be == (1 << 7),
|
||||
# Last data word, but all bytes were valid.
|
||||
).Elif(adjusted_sink_valid_last_be == (1 << 7),
|
||||
# Last data word, but all bytes were valid. Thus we still
|
||||
# need to transmit the XGMII end control character.
|
||||
NextValue(end_transmission, 1),
|
||||
NextValue(sink.ready, 0),
|
||||
NextState("TRANSMIT"),
|
||||
).Else(
|
||||
NextValue(sink.ready, 1),
|
||||
# We did already transmit the XGMII end control
|
||||
# character. Depending on the interframegap sent as part of
|
||||
# this cycle and the current deficit idle count, we might
|
||||
# already be able to accept data in the next clock cycle.
|
||||
If((next_ifg >= 2)
|
||||
| ((next_ifg == 1) & (last_packet_rem != 0)
|
||||
& (current_dic + last_packet_rem <= 3)),
|
||||
NextValue(sink.ready, 1),
|
||||
).Else(
|
||||
NextValue(sink.ready, 0),
|
||||
),
|
||||
NextState("IDLE"),
|
||||
)
|
||||
)
|
||||
|
|
@ -310,12 +653,19 @@ class LiteEthPHYXGMII(Module, AutoCSR):
|
|||
pads,
|
||||
model=False,
|
||||
dw=64,
|
||||
with_hw_init_reset=True):
|
||||
with_hw_init_reset=True,
|
||||
dic=True,
|
||||
):
|
||||
self.dw = dw
|
||||
self.cd_eth_tx, self.cd_eth_rx = "eth_tx", "eth_rx"
|
||||
self.integrated_ifg_inserter = True
|
||||
self.submodules.crg = LiteEthPHYXGMIICRG(clock_pads, model)
|
||||
self.submodules.tx = ClockDomainsRenamer(self.cd_eth_tx)(
|
||||
LiteEthPHYXGMIITX(pads, self.dw))
|
||||
LiteEthPHYXGMIITX(
|
||||
pads,
|
||||
self.dw,
|
||||
dic=dic,
|
||||
))
|
||||
self.submodules.rx = ClockDomainsRenamer(self.cd_eth_rx)(
|
||||
LiteEthPHYXGMIIRX(pads, self.dw))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
|
|||
Loading…
Reference in New Issue