ea0a65d357
Because XGMII only allows start of frame characters to be placed on lane 0 (first octet in a 32-bit XGMII bus word), when a packet's length % 4 != 0, we can't transmit exactly 12 XGMII idle characters inter-frame gap (the XGMII end of frame character counts towards the inter-frame gap, while start of frame does not). Given we are required to transmit a minimum of 12 bytes IFG, it's allowed to send packet length % 4 bytes additional IFG bytes. However this would waste precious bandwidth transmitting these characters. Thus, 10Gbit/s Ethernet and above allow using the deficit idle count mechanism. It allows to delete some idle characters, as long as an average count of >= 12 bytes IFG is maintained. This is to be implemented as a two bit counter as specified in IEEE802.3-2018, section four, 46.3.1.4 Start control character alignment. In practice, the previous implementation of the LiteEthPHYXGMIITX made these issues even more prevalent: because the internal stream interface is 64-bit wide and stream transactions always start aligned to the first octet in a bus word, the previous primitive TX implementation always started transmission on the first octet in the 64-bit XGMII bus word. The IFG inserter operated independently if the PHY and thus made sure to maintain 12 bytes of IFG on the 64-bit stream bus. This means that in a worst case scenario, the IFG could grow to 23 octets. In applications such as Ethernet switches, the consequences would be frequent buffer overruns or corrupt transmissions. Hence this commit introduces a IFG inserter in the LiteEthPHYXGMIITX module itself. It is significantly more complex compared to the gap inserter, but inserts the smallest legal gap as defined by IEEE802.3. Furthermore, it optionally implements the deficit idle count algorithm as described by Eric Lynskey of the UNH InterOperability Lab1 to achieve an average IFG of 12 bytes. Signed-off-by: Leon Schuermann <leon@is.currently.online> |
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| .github/workflows | ||
| bench | ||
| doc | ||
| examples | ||
| liteeth | ||
| test | ||
| .gitignore | ||
| CONTRIBUTORS | ||
| LICENSE | ||
| README.md | ||
| setup.py | ||
README.md
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Copyright 2012-2020 / EnjoyDigital
A small footprint and configurable Ethernet core
powered by Migen & LiteX
[> Intro
LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
Using Migen to describe the HDL allows the core to be highly and easily configurable.
LiteEth can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.
[> Features
PHY:
- MII, RMII 100Mbps PHYs.
- GMII / RGMII /1000BaseX 1Gbps PHYs.
Core:
- Configurable MAC (HW or SW interface)
- ARP / ICMP / UDP (HW or SW)
Frontend:
- Etherbone (Wishbone over UDP: Slave or Master support)
[> FPGA Proven
LiteEth is already used in commercial and open-source designs:
- MiSoC: http://m-labs.hk/gateware.html
- ARTIQ: http://m-labs.hk/artiq/index.html
- HDMI2USB: http://hdmi2usb.tv/home/
- and others commercial designs...
[> Possible improvements
- add standardized interfaces (AXI, Avalon-ST)
- add DMA interface to MAC
- add more documentation
- ... See below Support and consulting :)
If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.
[> Getting started
- Install Python 3.6+ and FPGA vendor's development tools.
- Install LiteX and the cores by following the LiteX's wiki installation guide.
- You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.
[> Tests
Unit tests are available in ./test/. To run all the unit tests:
$ ./setup.py test
Tests can also be run individually:
$ python3 -m unittest test.test_name
[> License
LiteEth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteEth for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:
- tell us that you are using LiteEth
- cite LiteEth in publications related to research it has helped
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteEth.
[> Support and consulting
We love open-source hardware and like sharing our designs with others.
LiteEth is developed and maintained by EnjoyDigital.
If you would like to know more about LiteEth or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard commercial support as well as consulting services.
So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :)
[> Contact
E-mail: florent [AT] enjoy-digital.fr