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phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by usign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-03 15:06:46 +02:00
parent 9780327251
commit ecaebfe645
1 changed files with 2 additions and 2 deletions
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liteeth/phy/trionrgmii.py
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@ -144,9 +144,9 @@ class LiteEthPHYRGMIICRG(LiteXModule):
# ------- # -------
self.pll = pll = TRIONPLL(platform) self.pll = pll = TRIONPLL(platform)
pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in") pll.register_clkin(None, freq=125e6, name=f"auto_eth{n}_rx_clk_in")
pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False) pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True)
pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False) pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0, name=f"auto_eth{n}_tx_clk", with_reset=False)
pll.create_clkout(None, freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed") pll.create_clkout(None, freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed")
# Reset. # Reset.
# ------ # ------