phy/usrgmii: improve presentation
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2bdae4e7bd
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@ -212,12 +212,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
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class LiteEthPHYRGMII(Module, AutoCSR):
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class LiteEthPHYRGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.dw = 8
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads,
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
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with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
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LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(
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LiteEthPHYRGMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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if hasattr(pads, "mdc"):
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