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phy/usrgmii: improve presentation

This commit is contained in:
Florent Kermarrec 2020-01-17 09:15:51 +01:00
parent 2bdae4e7bd
commit ee4f8c0f34
1 changed files with 15 additions and 18 deletions
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33
liteeth/phy/usrgmii.py
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@ -15,7 +15,7 @@ class LiteEthPHYRGMIITX(Module):
# # # # # #
tx_ctl_obuf = Signal() tx_ctl_obuf = Signal()
tx_data_obuf = Signal(4) tx_data_obuf = Signal(4)
self.specials += [ self.specials += [
@ -50,12 +50,12 @@ class LiteEthPHYRGMIIRX(Module):
# # # # # #
rx_ctl_ibuf = Signal() rx_ctl_ibuf = Signal()
rx_ctl_idelay = Signal() rx_ctl_idelay = Signal()
rx_ctl = Signal() rx_ctl = Signal()
rx_data_ibuf = Signal(4) rx_data_ibuf = Signal(4)
rx_data_idelay = Signal(4) rx_data_idelay = Signal(4)
rx_data = Signal(8) rx_data = Signal(8)
self.specials += [ self.specials += [
Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf), Instance("IBUF", i_I=pads.rx_ctl, o_O=rx_ctl_ibuf),
@ -137,8 +137,8 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
# # # # # #
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()
self.clock_domains.cd_eth_tx90 = ClockDomain(reset_less=True) self.clock_domains.cd_eth_tx90 = ClockDomain(reset_less=True)
# RX # RX
@ -153,10 +153,10 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
] ]
# TX # TX
pll_locked = Signal() pll_locked = Signal()
pll_fb = Signal() pll_fb = Signal()
pll_clk_tx = Signal() pll_clk_tx = Signal()
pll_clk_tx90 = Signal() pll_clk_tx90 = Signal()
eth_tx_clk_obuf = Signal() eth_tx_clk_obuf = Signal()
self.specials += [ self.specials += [
Instance("PLLE2_BASE", Instance("PLLE2_BASE",
@ -212,12 +212,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
class LiteEthPHYRGMII(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
with_hw_init_reset) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.tx = ClockDomainsRenamer("eth_tx")( self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(
LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source
if hasattr(pads, "mdc"): if hasattr(pads, "mdc"):