mac/core: Move preamble into switchable domain
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688011f936
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@ -37,6 +37,11 @@ class LiteEthMACCore(Module, AutoCSR):
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self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter)
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self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter)
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tx_pipeline += [tx_gap_inserter]
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tx_pipeline += [tx_gap_inserter]
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if sys_data_path:
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self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness)
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cd_tx = cd_rx = "sys"
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dw = core_dw
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# Preamble / CRC
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# Preamble / CRC
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if isinstance(phy, LiteEthPHYModel):
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if isinstance(phy, LiteEthPHYModel):
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# In simulation, avoid CRC/Preamble to enable direct connection
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# In simulation, avoid CRC/Preamble to enable direct connection
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@ -61,12 +66,6 @@ class LiteEthMACCore(Module, AutoCSR):
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self.sync += If(self.ps_preamble_error.o,
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self.sync += If(self.ps_preamble_error.o,
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self.preamble_errors.status.eq(self.preamble_errors.status + 1)),
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self.preamble_errors.status.eq(self.preamble_errors.status + 1)),
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if sys_data_path:
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self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness)
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cd_tx = cd_rx = "sys"
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dw = core_dw
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if not isinstance(phy, LiteEthPHYModel) and with_preamble_crc:
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# CRC insert/check
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# CRC insert/check
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crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(dw)))
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crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(dw)))
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crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(dw)))
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crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(dw)))
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