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Remove clock asserts 

They aren't strictly necessary, especially since the MAC can have
a wider data path and thus cope with running slightly slower

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2021-09-23 12:24:58 +10:00
parent 9b3837e636
commit f2032a4227
1 changed files with 0 additions and 5 deletions
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5
liteeth/gen.py
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@ -179,28 +179,23 @@ class PHYCore(SoCMini):
# PHY -------------------------------------------------------------------------------------- # PHY --------------------------------------------------------------------------------------
phy = core_config["phy"] phy = core_config["phy"]
if phy in [liteeth_phys.LiteEthPHYMII]: if phy in [liteeth_phys.LiteEthPHYMII]:
assert self.clk_freq >= 12.5e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("mii_eth_clocks"), clock_pads = platform.request("mii_eth_clocks"),
pads = platform.request("mii_eth")) pads = platform.request("mii_eth"))
elif phy in [liteeth_phys.LiteEthPHYRMII]: elif phy in [liteeth_phys.LiteEthPHYRMII]:
assert self.clk_freq >= 12.5e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("rmii_eth_clocks"), clock_pads = platform.request("rmii_eth_clocks"),
pads = platform.request("rmii_eth")) pads = platform.request("rmii_eth"))
elif phy in [liteeth_phys.LiteEthPHYGMII]: elif phy in [liteeth_phys.LiteEthPHYGMII]:
assert self.clk_freq >= 125e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("gmii_eth_clocks"), clock_pads = platform.request("gmii_eth_clocks"),
pads = platform.request("gmii_eth")) pads = platform.request("gmii_eth"))
elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: elif phy in [liteeth_phys.LiteEthPHYGMIIMII]:
assert self.clk_freq >= 125e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("gmii_eth_clocks"), clock_pads = platform.request("gmii_eth_clocks"),
pads = platform.request("gmii_eth"), pads = platform.request("gmii_eth"),
clk_freq = self.clk_freq) clk_freq = self.clk_freq)
elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]: elif phy in [liteeth_phys.LiteEthS7PHYRGMII, liteeth_phys.LiteEthECP5PHYRGMII]:
assert self.clk_freq >= 125e6
ethphy = phy( ethphy = phy(
clock_pads = platform.request("rgmii_eth_clocks"), clock_pads = platform.request("rgmii_eth_clocks"),
pads = platform.request("rgmii_eth"), pads = platform.request("rgmii_eth"),