update litex uart
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@ -4,7 +4,7 @@ from litex.build.xilinx.vivado import XilinxVivadoToolchain
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.cores.uart.bridge import UARTWishboneBridge
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from litex.soc.cores.uart import UARTWishboneBridge
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from liteeth.common import *
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from liteeth.common import *
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from liteeth.phy import LiteEthPHY
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from liteeth.phy import LiteEthPHY
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