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bench: Update.

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This commit is contained in:
Florent Kermarrec 2023-06-13 14:13:03 +02:00
parent 6d26f35ee4
commit fa08ce1ccc
9 changed files with 58 additions and 42 deletions
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16
bench/arty.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -13,6 +13,8 @@ from migen import *
from migen.genlib.cdc import MultiReg from migen.genlib.cdc import MultiReg
from migen.genlib.misc import WaitTimer from migen.genlib.misc import WaitTimer
from litex.gen import *
from litex_boards.platforms import digilent_arty from litex_boards.platforms import digilent_arty
from litex_boards.targets.digilent_arty import _CRG from litex_boards.targets.digilent_arty import _CRG
@ -37,10 +39,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYMII( self.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"), pads = self.platform.request("eth"),
with_hw_init_reset = False) with_hw_init_reset = False)
@ -51,8 +53,8 @@ class BenchSoC(SoCCore):
# UDP Streamer ----------------------------------------------------------------------------- # UDP Streamer -----------------------------------------------------------------------------
from liteeth.frontend.stream import LiteEthUDPStreamer from liteeth.frontend.stream import LiteEthUDPStreamer
self.submodules.udp_streamer = udp_streamer = LiteEthUDPStreamer( self.udp_streamer = udp_streamer = LiteEthUDPStreamer(
udp = self.ethcore.udp, udp = self.ethcore_etherbone.udp,
ip_address = "192.168.1.100", ip_address = "192.168.1.100",
udp_port = 6000, udp_port = 6000,
) )
@ -62,7 +64,7 @@ class BenchSoC(SoCCore):
# Led Chaser (Default). # Led Chaser (Default).
chaser_leds = Signal(len(leds_pads)) chaser_leds = Signal(len(leds_pads))
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = chaser_leds, pads = chaser_leds,
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
@ -74,7 +76,7 @@ class BenchSoC(SoCCore):
) )
# Led Mux: Switch to received UDP value for 1s then switch back to Led Chaser. # Led Mux: Switch to received UDP value for 1s then switch back to Led Chaser.
self.submodules.leds_timer = leds_timer = WaitTimer(sys_clk_freq) self.leds_timer = leds_timer = WaitTimer(sys_clk_freq)
self.comb += [ self.comb += [
leds_timer.wait.eq(~udp_streamer.rx.source.valid), # Reload Timer on new UDP value. leds_timer.wait.eq(~udp_streamer.rx.source.valid), # Reload Timer on new UDP value.
If(leds_timer.done, If(leds_timer.done,

12
bench/butterstick.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -11,6 +11,8 @@ import argparse
from migen import * from migen import *
from litex.gen import *
from litex_boards.platforms import gsd_butterstick from litex_boards.platforms import gsd_butterstick
from litex_boards.targets.gsd_butterstick import _CRG from litex_boards.targets.gsd_butterstick import _CRG
@ -34,10 +36,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII( self.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"), pads = self.platform.request("eth"),
tx_delay = 0e-9, tx_delay = 0e-9,
@ -50,7 +52,7 @@ class BenchSoC(SoCCore):
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
self.comb += platform.request("user_led_color").eq(0b010) # Blue. self.comb += platform.request("user_led_color").eq(0b010) # Blue.
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq sys_clk_freq = sys_clk_freq
) )
@ -62,7 +64,7 @@ class BenchSoC(SoCCore):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
ethcore = self.ethcore_etherbone ethcore = self.ethcore_etherbone
etherbone = self.etherbone etherbone = self.etherbone
self.submodules.analyzer = LiteScopeAnalyzer([ self.analyzer = LiteScopeAnalyzer([
# MAC. # MAC.
ethcore.mac.core.sink.valid, ethcore.mac.core.sink.valid,
ethcore.mac.core.sink.ready, ethcore.mac.core.sink.ready,

10
bench/colorlight_5a_75b.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -11,6 +11,8 @@ import argparse
from migen import * from migen import *
from litex.gen import *
from litex_boards.platforms import colorlight_5a_75b from litex_boards.platforms import colorlight_5a_75b
from litex_boards.targets.colorlight_5a_75x import _CRG from litex_boards.targets.colorlight_5a_75x import _CRG
@ -34,10 +36,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII( self.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"), pads = self.platform.request("eth"),
tx_delay = 0e-9, tx_delay = 0e-9,
@ -49,7 +51,7 @@ class BenchSoC(SoCCore):
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = platform.request_all("user_led_n"), pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)

10
bench/genesys2.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -11,6 +11,8 @@ import argparse
from migen import * from migen import *
from litex.gen import *
from litex_boards.platforms import digilent_genesys2 from litex_boards.platforms import digilent_genesys2
from litex_boards.targets.digilent_genesys2 import _CRG from litex_boards.targets.digilent_genesys2 import _CRG
@ -34,10 +36,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYRGMII( self.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"), pads = self.platform.request("eth"),
with_hw_init_reset = False) with_hw_init_reset = False)
@ -48,7 +50,7 @@ class BenchSoC(SoCCore):
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)

18
bench/kcu105.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2021-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -12,6 +12,8 @@ import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.gen import *
from litex_boards.platforms import xilinx_kcu105 from litex_boards.platforms import xilinx_kcu105
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
@ -23,15 +25,15 @@ from liteeth.phy.ku_1000basex import KU_1000BASEX
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module, AutoCSR): class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.cd_eth = ClockDomain()
# # # # # #
# Main PLL. # Main PLL.
self.submodules.main_pll = main_pll = USMMCM(speedgrade=-2) self.main_pll = main_pll = USMMCM(speedgrade=-2)
self.comb += main_pll.reset.eq(platform.request("cpu_reset")) self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
main_pll.register_clkin(platform.request("clk125"), 125e6) main_pll.register_clkin(platform.request("clk125"), 125e6)
main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_sys, sys_clk_freq)
@ -50,10 +52,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk, self.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("sfp", 0), data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq) sys_clk_freq = self.clk_freq)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
@ -65,7 +67,7 @@ class BenchSoC(SoCCore):
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)

10
bench/sim.py
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@ -3,13 +3,15 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import argparse import argparse
from migen import * from migen import *
from litex.gen import *
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex.build.sim import SimPlatform from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig from litex.build.sim.config import SimConfig
@ -22,8 +24,10 @@ from liteeth.phy.model import LiteEthPHYModel
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
# Sys Clk/Rst.
("sys_clk", 0, Pins(1)), ("sys_clk", 0, Pins(1)),
("sys_rst", 0, Pins(1)), ("sys_rst", 0, Pins(1)),
# Ethernet.
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("tx", Pins(1)), Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)), Subsignal("rx", Pins(1)),
@ -59,10 +63,10 @@ class BenchSoC(SoCCore):
) )
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk")) self.crg = CRG(platform.request("sys_clk"))
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) self.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.add_etherbone(phy=self.ethphy, buffer_depth=255) self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM ------------------------------------------------------------------------------------- # SRAM -------------------------------------------------------------------------------------

2
bench/test_etherbone.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteEth # This file is part of LiteEth
# #
# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
# LiteEth Etherbone test utility. # LiteEth Etherbone test utility.

2
bench/test_udp_streamer.py
View file

@ -3,7 +3,7 @@
# #
# This file is part of LiteEth # This file is part of LiteEth
# #
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2021-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
# LiteEth UDP Streamer test utility. # LiteEth UDP Streamer test utility.

20
bench/xcu1525.py
View file

@ -3,7 +3,7 @@
# #
# This file is part of LiteEth. # This file is part of LiteEth.
# #
# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2021-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -12,6 +12,8 @@ import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.gen import *
from litex.build.generic_platform import * from litex.build.generic_platform import *
from litex_boards.platforms import sqrl_xcu1525 from litex_boards.platforms import sqrl_xcu1525
@ -37,15 +39,15 @@ _qsfp_io = [
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module, AutoCSR): class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.cd_eth = ClockDomain()
# # # # # #
# Main PLL. # Main PLL.
self.submodules.main_pll = main_pll = USPMMCM(speedgrade=-2) self.main_pll = main_pll = USPMMCM(speedgrade=-2)
main_pll.register_clkin(platform.request("clk300"), 300e6) main_pll.register_clkin(platform.request("clk300"), 300e6)
main_pll.create_clkout(self.cd_sys, sys_clk_freq) main_pll.create_clkout(self.cd_sys, sys_clk_freq)
main_pll.create_clkout(self.cd_eth, 200e6) main_pll.create_clkout(self.cd_eth, 200e6)
@ -67,10 +69,10 @@ class BenchSoC(SoCCore):
self.add_uartbone() self.add_uartbone()
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)
# Etherbone -------------------------------------------------------------------------------- # Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = USP_1000BASEX(self.crg.cd_eth.clk, self.ethphy = USP_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("qsfp", 0), data_pads = self.platform.request("qsfp", 0),
sys_clk_freq = self.clk_freq) sys_clk_freq = self.clk_freq)
self.comb += self.platform.request("qsfp_fs").eq(0b01) self.comb += self.platform.request("qsfp_fs").eq(0b01)
@ -81,7 +83,7 @@ class BenchSoC(SoCCore):
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser( self.leds = LedChaser(
pads = platform.request_all("user_led"), pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq sys_clk_freq = sys_clk_freq
) )
@ -90,7 +92,7 @@ class BenchSoC(SoCCore):
from litescope import LiteScopeAnalyzer from litescope import LiteScopeAnalyzer
analyzer_signals = self.ethphy.debug analyzer_signals = self.ethphy.debug
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, self.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256, depth = 256,
clock_domain = "sys", clock_domain = "sys",
csr_csv = "analyzer.csv" csr_csv = "analyzer.csv"