Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
628 Commits 6 Branches 14 Tags 3.6 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Victor Suarez Rovere 5f14bd4a7f add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file) 2022-10-31 20:43:53 -03:00