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  • 49c62e6557
         Merge d0608e6756 into 3897ed022c david-sawatzke 2024-12-18 18:24:38 +0100
  • 3897ed022c
         Merge pull request #178 from FlyGoat/CPLLREFCLKSEL master enjoy-digital 2024-12-18 11:30:50 +0100
  • 76db5e12a0
         Merge 1b09112237 into d2b1b0e0c5 Rowan Goemans 2024-12-16 15:56:11 +0000
  • 50ad88cc85 phy/usp_gth/gty_1000basex: Set proper CPLLREFCLKSEL for refclk_from_fabric Jiaxun Yang 2024-12-16 15:50:58 +0000
  • d2b1b0e0c5 frontend/stream: Add default ip_address/udp_port values. Florent Kermarrec 2024-12-16 14:45:45 +0100
  • aad9de7e53 frontend/stream/LiteEthStream2UDPTX: Add optional CSR to allow dynamic configuration (Enable, IP Address and UDP Port). Florent Kermarrec 2024-12-13 21:27:47 +0100
  • 9f4d9d20bc phy: Add initial Ultrascale+ GTYE4 10GBASE-R PHY. Florent Kermarrec 2024-12-12 14:41:21 +0100
  • 0685079333 liteeth/phy/1000basex: Avoid splitting transceiver instance since no longer useful with current Python version. Florent Kermarrec 2024-12-12 14:17:23 +0100
  • d0608e6756 mac/core: Allow using core_dw smaller than phy_dw David Sawatzke 2024-12-11 10:59:23 +0100
  • 032266acf3
         Merge f630a6f8d5 into 99d4073c6a sergpolkin 2024-11-26 20:51:39 +0000
  • 99d4073c6a phy/usp_gth/gty_1000basex: Add refclk_from_fabric parameter to allow selecting GTGREFCLK or GTREFCLK0. Florent Kermarrec 2024-11-25 09:21:17 +0100
  • 17f80af672 liteeth/gen: Cosmetic cleanup in 1000BaseX. Florent Kermarrec 2024-11-25 09:07:53 +0100
  • 1bbb735f9f phy/pcs_1000basex: Cleanup PCSRX buffer and fix PCS TX ready on Start-of-packet. Florent Kermarrec 2024-10-18 18:27:54 +0200
  • a58e25c2f0 phy/pcs_1000basex: Remove rx_config_reg_ack.o check in AUTONEG-WAIT-ABI since no longer useful. Florent Kermarrec 2024-10-18 14:23:14 +0200
  • b783639889 phy/pcs_1000basex: Add specific breaklink timer and increase consistency count to 8. Florent Kermarrec 2024-10-18 14:18:24 +0200
  • 20e9ea6656 phy/pcs_1000basex: Refactor/Simplify RX Config consistency check. Florent Kermarrec 2024-10-16 11:23:54 +0200
  • 2a7df9cbba phy/pcs_1000basex: Cleanup pass. Florent Kermarrec 2024-10-16 10:44:40 +0200
  • cd2274d905 phy/pcs1000basex: Improve/Simplify PCSRX source logic. Florent Kermarrec 2024-10-16 10:12:23 +0200
  • 93472ef2d6 phy/pcs_1000basex/PCS: Another cleanup pass. Florent Kermarrec 2024-10-15 21:51:27 +0200
  • aa9c40988b phy/pcs_1000basex: Add PCSSGMIITimer and share it between PCSTX/PCSRX. Florent Kermarrec 2024-10-15 21:38:03 +0200
  • fe69248ff3 phy/pcs_1000basex/PCS: Cleanup checker signal names, avoid ceil on timer values since this level of precision is not relevant. Florent Kermarrec 2024-10-15 21:27:01 +0200
  • 01b91a3fd0 phy/pcs_1000basex: Replace PCSRX rx_en/data with stream.Endpoint and cosmetic cleanup. Florent Kermarrec 2024-10-15 21:20:40 +0200
  • 9a123136e7 phy/pcs_1000basex: Update copyrights. Florent Kermarrec 2024-10-15 12:56:25 +0200
  • efcbebe558
         Merge pull request #174 from enjoy-digital/1000basex_fixes_cleanup enjoy-digital 2024-10-15 12:51:58 +0200
  • 16998377f6 phy/pcs_1000basex: Simplify/Cleanup PCSRX. 1000basex_fixes_cleanup Florent Kermarrec 2024-10-15 11:54:31 +0200
  • faf426f54a phy/pcs_1000basex: Other cosmetic cleanup on PCSTX. Florent Kermarrec 2024-10-15 11:46:39 +0200
  • 19e1d19444 phy/pcs_1000basex: Move PCS Gearbox. Florent Kermarrec 2024-10-15 11:40:13 +0200
  • 313e7a985c phy/pcs_1000basex: Simplify/Cleanup PCSTX. Florent Kermarrec 2024-10-15 10:19:53 +0200
  • 8a3e0a23aa phy/a7_1000basex: Use ALIGN_COMMA_WORD/RXCDR_CFG from Xilinx wizard. Florent Kermarrec 2024-10-15 10:06:45 +0200
  • 04fc888285 liteeth/phy/pcs_1000basex: Avoid deadlock situation in AUTONEG_WAIT_ABI if receiving ACKNOWLEDGE instead of ABILITY. Florent Kermarrec 2024-10-15 09:52:15 +0200
  • e5746c8a81 phy/pcs_1000basex: Add missing RX Align during AUTONEG_WAIT_ABI state and enable/connect it on all PHYs. Florent Kermarrec 2024-10-15 09:47:46 +0200
  • 7e602c406d phy/pcs_1000basex: Replace self.lp_abi.o[0] with is_sgmii to ease understanding. Florent Kermarrec 2024-10-15 09:28:09 +0200
  • 41c8b50ba5 phy/pcs_1000basex: Cleanup sgmii timer reload. Florent Kermarrec 2024-10-15 09:26:34 +0200
  • 78b8f9ee85 mac/sram: Minor cosmetic cleanup. Florent Kermarrec 2024-10-15 09:17:42 +0200
  • 4334547afe
         Merge 82d5f641e5 into b96a6252c4 Rowan Goemans 2024-09-29 02:58:16 -0400
  • f30d6ef7b9 mac/core: Switch to LiteXModule. Florent Kermarrec 2024-09-27 15:14:23 +0200
  • b96a6252c4 setup.py: 2024.08 release. 2024.08 Florent Kermarrec 2024-09-27 09:35:27 +0200
  • 880bdf43b0 liteeth/phy/rmii: Add 10Mbps/100MBps dynamic speed support. Florent Kermarrec 2024-09-26 12:57:29 +0200
  • 7f91ebbee5
         Merge pull request #172 from VOGL-electronic/phy_rmii_fix_efinix_sdr enjoy-digital 2024-09-26 11:55:32 +0200
  • 90b1a18485
         Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll enjoy-digital 2024-09-26 11:51:44 +0200
  • 3696ef82bb phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL Gwenhael Goavec-Merou 2024-09-26 11:03:12 +0200
  • 3693c61cbe
         phy/rmii: fix it for efinix Fin Maaß 2024-09-25 17:06:29 +0200
  • 2b0156e9b3 liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding parameters. Florent Kermarrec 2024-09-23 16:35:28 +0200
  • 1d19de09ef phy/rmii: Cosmetic cleanups. Florent Kermarrec 2024-09-23 15:30:08 +0200
  • f252eed154 phy/rmii/LiteEthPHYRMIIRX: Avoid FSM, simplify and add comments. Florent Kermarrec 2024-09-23 14:55:10 +0200
  • 5438ff01e1 phy/rmii/LiteEthPHYRMIIRX: Avoid reset on converter and improve frame delimitation. Florent Kermarrec 2024-09-23 12:22:57 +0200
  • 66b277a80b phy/rmii: Also use SDROutput on TX and add comments/simplify. Florent Kermarrec 2024-09-23 11:53:42 +0200
  • 3cfbf007ab phy/rmii/LiteEthPHYRMIIRX: Use SDRInput on pads.csr_dv/rx_data to make it clear input is synchronous. Florent Kermarrec 2024-09-23 11:42:30 +0200
  • 5538c87115 liteeth/phy/rmii: Move crs first/last detection outside of FSM. Florent Kermarrec 2024-09-23 11:30:57 +0200
  • 1c89387d09 liteeth/phy/rmii: Replace MuliReg with stream.Delay. Florent Kermarrec 2024-09-23 11:05:23 +0200
  • af746ec973 liteeth/core/__init__.py: Switch to LiteXModule. Florent Kermarrec 2024-09-20 16:19:03 +0200
  • a75f4e5ea7 CONTRIBUTORS: Update. Florent Kermarrec 2024-09-20 12:28:14 +0200
  • 28cf1c267b LICENSE/README.md: Bump year. Florent Kermarrec 2024-09-20 12:27:07 +0200
  • dd1988a40d frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case. Florent Kermarrec 2024-09-20 12:15:18 +0200
  • d5a9f9d2d4 core: Expose icmp_fifo_depth paramter. Florent Kermarrec 2024-09-19 22:18:53 +0200
  • b61c3e5bd1
         Merge pull request #171 from GustavsC/master enjoy-digital 2024-09-18 11:19:01 +0200
  • db1795171b
         Merge branch 'enjoy-digital:master' into master Gustav 2024-09-17 16:56:26 -0300
  • 5bc0ec00be
         Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix enjoy-digital 2024-09-17 21:20:30 +0200
  • ac70566ab4 Create v7_1000basex.py GustavsC 2024-09-17 11:24:38 -0300
  • b573e1267c phy/xgmii: Add Clk/Data Pads definition to avoid duplication in PHYs. Florent Kermarrec 2024-09-16 11:35:33 +0200
  • 7e072a997b
         phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput Fin Maaß 2024-09-13 12:05:38 +0200
  • 78513c2ba7 frontend/stream: Add 64-bit data_width support. Florent Kermarrec 2024-09-12 18:46:11 +0200
  • b1f916a447 frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketRX for 64-bit data-width support. Florent Kermarrec 2024-09-12 13:33:39 +0200
  • 0b5389feab mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler. Florent Kermarrec 2024-09-12 13:32:38 +0200
  • a2a862dc1b liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally). Florent Kermarrec 2024-09-11 15:21:24 +0200
  • 74bd085757
         Merge pull request #168 from trabucayre/efinix_rework_primitives Gwenhael Goavec-Merou 2024-09-10 18:41:06 +0200
  • 9496fd229f phy/titaniumrgmii.py: uses ClockSignal for DDRInput/DDROutput/ClkOutput, added cd for eth_tx_delayed, removed name=xxx for clkout with a cd Gwenhael Goavec-Merou 2024-09-10 11:52:48 +0200
  • 88387cbd11 phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter when a cd is used Gwenhael Goavec-Merou 2024-09-10 11:27:47 +0200
  • 577a47222c phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal Gwenhael Goavec-Merou 2024-09-10 08:09:03 +0200
  • ea07f5c421 phy/titaniumrgmii,trionrgmii: fixed pll clkin name by appending a '0' to match ClkInput / get_pin_name modifications introduces by LiteX commit d3161ad74c4b2afd5635f76f566c37f362eb166a Gwenhael Goavec-Merou 2024-09-04 14:48:34 +0200
  • ecaebfe645 phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by usign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45 Gwenhael Goavec-Merou 2024-09-03 15:06:46 +0200
  • 9780327251
         Merge pull request #167 from VOGL-electronic/fix_liteethmac enjoy-digital 2024-08-27 09:20:33 +0200
  • 7086f6d0ea
         mac/__init__.py: Fix LiteEthMAC. Fin Maaß 2024-08-27 08:41:26 +0200
  • edc7188faa mac/__init__.py: Improve/Cleanup LiteEthMAC. Florent Kermarrec 2024-08-19 10:19:53 +0200
  • bfc07e543a mac/__init__: Add comments on RX broadcard/filtering and minor cleanups. Florent Kermarrec 2024-08-19 09:58:53 +0200
  • 0bb6c53795 mac/__init__.py: Switch to LiteXModule and cosmetic improvements. Florent Kermarrec 2024-08-19 09:38:35 +0200
  • 55bae6b7b4
         Merge pull request #165 from VOGL-electronic/fix_packet_handling enjoy-digital 2024-08-19 09:27:54 +0200
  • 9531af62a7
         Merge pull request #166 from VOGL-electronic/fix_etherbone enjoy-digital 2024-08-19 09:26:25 +0200
  • 964df3ac2f phy/a7_gtp: Add separators and remove __all__. Florent Kermarrec 2024-08-19 09:23:38 +0200
  • c04ac8f698
         Merge pull request #164 from VOGL-electronic/optional_liteiclink enjoy-digital 2024-08-19 09:17:01 +0200
  • d4fa6a2f4a phy/a7_gtp: Add additionnal comment to #163 and express delay in us. Florent Kermarrec 2024-08-19 09:16:20 +0200
  • 32df4523ba
         Merge pull request #163 from cyntem/patch-1 enjoy-digital 2024-08-19 09:14:05 +0200
  • 7b4429e814 Fix etherbone reads Matthias Breithaupt 2024-08-18 17:20:05 +0200
  • da6e053f78 mac: implement mac filtering for logic interface in hybrid mode Matthias Breithaupt 2024-07-22 11:44:30 +0200
  • 85c3ab2c51 Only import liteiclink when required Matthias Breithaupt 2024-07-14 22:36:26 +0200
  • 4653a09aec
         Update a7_gtp.py cyntem 2024-07-14 20:05:00 +0300
  • b6ce406a9e
         Merge 0f78f12651 into 583137eaf3 Xiretza 2024-07-13 22:47:02 +0200
  • 583137eaf3 phy/1000basex: Use pll.config["d"] to compute TX_PROGDIV_CFG/RX_PROGDIV_CFG to fix behavior with 200MHz ref_clk_freq. Florent Kermarrec 2024-07-10 16:21:11 +0200
  • e0f053e7a2 bench: Set margin to 0 on 1000/2500BaseX reference clock generation. Florent Kermarrec 2024-07-10 15:39:04 +0200
  • 08c10774b5 phy/xgmii: Switch to LiteXModule and some cleanups. Florent Kermarrec 2024-07-10 11:56:08 +0200
  • ec7320f003 mac/wishbone: Fix ntxslots/nrxslots == 1 case. Florent Kermarrec 2024-07-02 13:50:06 +0200
  • a00640bf67 liteeth/mac/sram: Switch to LiteXModule. Florent Kermarrec 2024-06-26 15:44:30 +0200
  • e4f5385ef1
         Merge pull request #161 from enjoy-digital/wishbone_tx_rx_buses enjoy-digital 2024-06-25 19:04:38 +0200
  • a118dd146f liteeth/gen: Update MACCore with EthMAC changes. wishbone_tx_rx_buses Florent Kermarrec 2024-06-25 18:53:42 +0200
  • 80bded4ffc liteeth/mac/wishbone: Fix write_only mode on RX. Florent Kermarrec 2024-06-25 18:26:20 +0200
  • ec05e9c35c liteeth/mac/wishbone: Update copyrights. Florent Kermarrec 2024-06-25 18:17:02 +0200
  • 0e3e645b44 test/test_mac_wishbone: Update with TX/RX slot changes. Florent Kermarrec 2024-06-25 18:16:47 +0200
  • 591b77e991 mac/wishbone: Switch to LiteXModule. Florent Kermarrec 2024-06-25 17:57:16 +0200
  • 20e892c214 mac/wishbone: Add _expose_wishbone_sram_interfaces to avoid duplicating code between TX and RX. Florent Kermarrec 2024-06-25 17:56:12 +0200
  • 151b421a2c mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishbone buses to allow simultaneous TX/RX SRAM accesses. Florent Kermarrec 2024-06-25 17:36:18 +0200