mirror of
https://github.com/enjoy-digital/liteeth.git
synced 2025-01-03 03:43:37 -05:00
133 lines
4.2 KiB
Python
133 lines
4.2 KiB
Python
from liteeth.common import *
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from litex.gen.genlib.cdc import MultiReg
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from litex.gen.genlib.misc import WaitTimer
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from litex.gen.genlib.io import DDROutput
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from litex.gen.genlib.resetsync import AsyncResetSynchronizer
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from liteeth.phy.common import *
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def converter_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout, packetized=True)
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class LiteEthPHYRMIITX(Module):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_phy_description(8))
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# # #
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converter = Converter(converter_description(8),
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converter_description(2))
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self.submodules += converter
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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converter.sink.data.eq(sink.data),
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sink.ack.eq(converter.sink.ack),
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converter.source.ack.eq(1)
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]
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self.sync += [
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pads.tx_en.eq(converter.source.stb),
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pads.tx_data.eq(converter.source.data)
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]
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class LiteEthPHYRMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_phy_description(8))
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# # #
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sop = Signal(reset=1)
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sop_set = Signal()
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sop_clr = Signal()
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self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0))
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converter = Converter(converter_description(2),
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converter_description(8))
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converter = ResetInserter()(converter)
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self.submodules += converter
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converter_sink_stb = Signal()
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converter_sink_sop = Signal()
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converter_sink_data = Signal(2)
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self.specials += [
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MultiReg(converter_sink_stb, converter.sink.stb, n=2),
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MultiReg(converter_sink_sop, converter.sink.sop, n=2),
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MultiReg(converter_sink_data, converter.sink.data, n=2)
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]
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crs_dv = Signal()
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crs_dv_d = Signal()
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rx_data = Signal(2)
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self.sync += [
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crs_dv.eq(pads.crs_dv),
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crs_dv_d.eq(crs_dv),
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rx_data.eq(pads.rx_data)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(crs_dv & (rx_data != 0b00),
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converter_sink_stb.eq(1),
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converter_sink_sop.eq(1),
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converter_sink_data.eq(rx_data),
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NextState("RECEIVE")
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).Else(
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converter.reset.eq(1)
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)
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)
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fsm.act("RECEIVE",
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converter_sink_stb.eq(1),
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converter_sink_data.eq(rx_data),
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# end of frame when 2 consecutives 0 on crs_dv
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If(~(crs_dv | crs_dv_d),
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converter.sink.eop.eq(1),
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NextState("IDLE")
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)
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)
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self.comb += Record.connect(converter.source, source)
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class LiteEthPHYRMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset):
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self._reset = CSRStorage()
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# # #
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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self.comb += [
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self.cd_eth_rx.clk.eq(ClockSignal("eth")),
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self.cd_eth_tx.clk.eq(ClockSignal("eth"))
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]
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self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx"))
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reset = Signal()
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if with_hw_init_reset:
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self.submodules.hw_reset = LiteEthPHYHWReset()
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self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
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else:
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self.comb += reset.eq(self._reset.storage)
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYRMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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self.submodules.mdio = LiteEthPHYMDIO(pads)
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