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phy/common: add LiteEthPHYHWReset and use it on phys

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This commit is contained in:
Florent Kermarrec 2015-12-09 16:57:02 +01:00
parent 54d7c6620b
commit 1f19518d63
6 changed files with 46 additions and 60 deletions
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16
liteeth/phy/common.py
View file

@ -3,6 +3,22 @@ from liteeth.common import *
from litex.gen.genlib.cdc import MultiReg
from litex.gen.fhdl.specials import Tristate
class LiteEthPHYHWReset(Module):
def __init__(self):
self.reset = Signal()
# # #
counter = Signal(max=512)
counter_done = Signal()
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
self.reset.eq(~counter_done)
]
class LiteEthPHYMDIO(Module, AutoCSR):
def __init__(self, pads):

18
liteeth/phy/gmii.py
View file

@ -3,7 +3,7 @@ from liteeth.common import *
from litex.gen.genlib.io import DDROutput
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from liteeth.phy.common import LiteEthPHYMDIO
from liteeth.phy.common import *
class LiteEthPHYGMIITX(Module):
@ -73,19 +73,13 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
i_S=mii_mode,
o_O=self.cd_eth_tx.clk)
reset = Signal()
if with_hw_init_reset:
reset = Signal()
counter = Signal(max=512)
counter_done = Signal()
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
reset = self._reset.storage
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),

18
liteeth/phy/mii.py
View file

@ -2,7 +2,7 @@ from liteeth.common import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from liteeth.phy.common import LiteEthPHYMDIO
from liteeth.phy.common import *
def converter_description(dw):
@ -83,19 +83,13 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
reset = Signal()
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
counter = Signal(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
reset = self._reset.storage
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),

18
liteeth/phy/rmii.py
View file

@ -5,7 +5,7 @@ from litex.gen.genlib.misc import WaitTimer
from litex.gen.genlib.io import DDROutput
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from liteeth.phy.common import LiteEthPHYMDIO
from liteeth.phy.common import *
def converter_description(dw):
@ -107,19 +107,13 @@ class LiteEthPHYRMIICRG(Module, AutoCSR):
self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx"))
reset = Signal()
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
counter = Signal(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
reset = self._reset.storage
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),

18
liteeth/phy/s6rgmii.py
View file

@ -7,7 +7,7 @@ from litex.gen.genlib.fsm import FSM, NextState
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from liteeth.phy.common import LiteEthPHYMDIO
from liteeth.phy.common import *
class LiteEthPHYRGMIITX(Module):
@ -134,19 +134,13 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk)
# Reset
reset = Signal()
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
counter = Signal(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
reset = self._reset.storage
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),

18
liteeth/phy/s7rgmii.py
View file

@ -7,7 +7,7 @@ from litex.gen.genlib.fsm import FSM, NextState
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from liteeth.phy.common import LiteEthPHYMDIO
from liteeth.phy.common import *
class LiteEthPHYRGMIITX(Module):
@ -149,19 +149,13 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
]
# Reset
reset = Signal()
if with_hw_init_reset:
reset = Signal()
counter_done = Signal()
counter = Signal(max=512)
counter_ce = Signal()
self.sync += If(counter_ce, counter.eq(counter + 1))
self.comb += [
counter_done.eq(counter == 256),
counter_ce.eq(~counter_done),
reset.eq(~counter_done | self._reset.storage)
]
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
reset = self._reset.storage
self.comb += reset.eq(self._reset.storage)
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),