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Small footprint and configurable Ethernet core
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Arne Jansen 2b6d4ee51b wishbone: fix race condition in rx path 
When no rx slot is available, the current code path sends the FSM through
DISCARD-REMAINING to TERMINATE, which tries to signal the slot to the user
even though nothing has been received. This can lead to data corruption.
 		2022-12-08 17:58:25 +01:00
.github/workflows ci: Bump to ubuntu 20.04. 2022-10-14 18:17:35 +02:00
bench bench: Use full imports. 2022-05-02 13:09:28 +02:00
doc doc: add simple architecture diagram 2017-11-13 17:39:09 +01:00
examples add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file) 2022-10-31 20:43:53 -03:00
liteeth wishbone: fix race condition in rx path 2022-12-08 17:58:25 +01:00
test test_xgmii_phy: remove vcd dump of XGMII test 2021-11-21 19:28:26 +01:00
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setup.py setup.py: simplify, switch to Python3.6+ (using python_requires), remove version. 2020-04-07 11:54:31 +02:00

README.md 

                                      __   _ __      ______  __
                                     / /  (_) /____ / __/ /_/ /
                                    / /__/ / __/ -_) _// __/ _ \
                                   /____/_/\__/\__/___/\__/_//_/

                                 Copyright 2012-2022 / EnjoyDigital

                             A small footprint and configurable Ethernet core
                                      powered by Migen & LiteX

License

[> Intro

LiteEth provides a small footprint and configurable Ethernet core.

LiteEth is part of LiteX libraries whose aims are to lower entry level of complex FPGA cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...

Using Migen to describe the HDL allows the core to be highly and easily configurable.

LiteEth can be used as LiteX library or can be integrated with your standard design flow by generating the verilog rtl that you will use as a standard core.

[> Features

PHY:

  • MII, RMII 100Mbps PHYs.
  • GMII / RGMII /1000BaseX 1Gbps PHYs.

Core:

  • Configurable MAC (HW or SW interface)
  • ARP / ICMP / UDP (HW or SW)

Frontend:

  • Etherbone (Wishbone over UDP: Slave or Master support)

[> FPGA Proven

LiteEth is already used in commercial and open-source designs:

[> Possible improvements

  • add standardized interfaces (AXI, Avalon-ST)
  • add DMA interface to MAC
  • add more documentation
  • ... See below Support and consulting :)

If you want to support these features, please contact us at florent [AT] enjoy-digital.fr.

[> Getting started

  1. Install Python 3.6+ and FPGA vendor's development tools.
  2. Install LiteX and the cores by following the LiteX's wiki installation guide.
  3. You can find examples of integration of the core with LiteX in LiteX-Boards and in the examples directory.

[> Tests

Unit tests are available in ./test/. To run all the unit tests:

$ ./setup.py test

Tests can also be run individually:

$ python3 -m unittest test.test_name

[> License

LiteEth is released under the very permissive two-clause BSD license. Under the terms of this license, you are authorized to use LiteEth for closed-source proprietary designs. Even though we do not require you to do so, those things are awesome, so please do them if possible:

  • tell us that you are using LiteEth
  • cite LiteEth in publications related to research it has helped
  • send us feedback and suggestions for improvements
  • send us bug reports when something goes wrong
  • send us the modifications and improvements you have done to LiteEth.

[> Support and consulting

We love open-source hardware and like sharing our designs with others.

LiteEth is developed and maintained by EnjoyDigital.

If you would like to know more about LiteEth or if you are already a happy user and would like to extend it for your needs, EnjoyDigital can provide standard commercial support as well as consulting services.

So feel free to contact us, we'd love to work with you! (and eventually shorten the list of the possible improvements :)

[> Contact

E-mail: florent [AT] enjoy-digital.fr