liteeth/examples/wishbone_mii.yml
Xiretza 7a44209f77
Make memory/CSR regions customizable in config
Also remove interrupt mapping, since it's unused without a CPU anyway.
2020-02-12 15:55:04 +01:00

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YAML

# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
# PHY ----------------------------------------------------------------------
phy: LiteEthPHYMII
vendor: xilinx
# Core ---------------------------------------------------------------------
clk_freq: 100e6
core: wishbone
endianness: big
mem_map:
ethmac: 0x50000000