liteeth/bench
Florent Kermarrec 028838e744 phy/usp_1000basex: Update parameters from Xilinx PMA/PCS core. 2023-06-12 16:28:17 +02:00
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arty.py bench: Use full imports. 2022-05-02 13:09:28 +02:00
butterstick.py bench/butterstick: Add JTAGBone and Analyzer in MAC/ARP/IP/UDP/Etherbone control path. 2022-04-25 15:38:55 +02:00
colorlight_5a_75b.py bench: Update (remove calls to add_csr no longer required). 2021-07-02 09:34:33 +02:00
genesys2.py bench: Use full imports. 2022-05-02 13:09:28 +02:00
kcu105.py bench: Use full imports. 2022-05-02 13:09:28 +02:00
sim.py bench: Update (remove calls to add_csr no longer required). 2021-07-02 09:34:33 +02:00
test_etherbone.py bench/test_etherbone/speed_test: use burst_size of 255. 2020-11-26 11:36:12 +01:00
test_udp_streamer.py bench/arty:bench/arty: Add UDP Streamer example with UDP TX stream from Switches. 2021-09-22 18:21:20 +02:00
xcu1525.py phy/usp_1000basex: Update parameters from Xilinx PMA/PCS core. 2023-06-12 16:28:17 +02:00