liteeth/liteeth
Florent Kermarrec 9d13f612c1 core/arp: Fix missing set of response.mac_address in UPDATE_TABLE and reset update_count at the end of CLEAR state.
Fixes #147.
2023-10-11 09:09:02 +02:00
..
core core/arp: Fix missing set of response.mac_address in UPDATE_TABLE and reset update_count at the end of CLEAR state. 2023-10-11 09:09:02 +02:00
frontend frontend/stream/LiteEthStream2UDPTX: Latch ip_address/udp_port in Idle state. 2023-07-18 16:38:13 +02:00
mac mac/sram: Minor cleanup by directly using port instead of ports[n] in the loop. 2023-10-10 14:55:26 +02:00
phy phy/efinix: Use new LiteX's ClkInput/Output abstraction to simplify code/avoid duplications. 2023-09-12 09:34:43 +02:00
software software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default). 2020-11-24 19:40:18 +01:00
__init__.py init repo 2015-09-07 13:29:34 +02:00
common.py core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth. 2023-07-10 11:13:52 +02:00
crossbar.py crossbar: Switch to LiteXModule. 2023-07-10 09:53:45 +02:00
gen.py Merge pull request #137 from rowanG077/udpraw 2023-07-21 15:05:24 +02:00
packet.py packet: Switch to LiteX/Module. 2023-07-10 10:24:37 +02:00