liteeth/liteeth/mac
2020-03-13 15:30:36 +01:00
..
__init__.py mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone 2020-03-13 15:30:36 +01:00
common.py global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links 2019-11-21 11:01:55 +01:00
core.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
crc.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
gap.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
last_be.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
padding.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
preamble.py add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
sram.py mac/sram: simplify code and improve SRAM read speed using async_read on Memory. 2020-02-07 11:40:14 +01:00
wishbone.py mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful) 2019-11-23 00:12:46 +01:00