liteeth/liteeth
2022-04-25 15:55:59 +02:00
..
core core/icmp/LiteEthICMPEcho: Revert to PacketFIFO now that issue is understood. 2022-04-25 15:55:59 +02:00
frontend frontend/etherbone: Add assert on buffer_depth to prevent miss-configuration. 2022-04-08 09:27:52 +02:00
mac phy/xgmii: handle IFG insertion in PHY, support deficit idle count 2021-11-17 20:50:06 +01:00
phy phy/1000basex: Add crg_reset CSR for consistency with other PHYs. 2022-03-23 08:44:52 +01:00
software software/dissector: merge bit.lua/etherbone.lua in a single script and enable dissector on UDP port 1234 (LiteX's default). 2020-11-24 19:40:18 +01:00
__init__.py init repo 2015-09-07 13:29:34 +02:00
common.py core/ip/tx: Add broadcast capability. 2022-02-16 14:12:46 +01:00
crossbar.py crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design. 2022-01-26 10:51:07 +01:00
gen.py liteeth_gen/udp: Improve flexibility and add support for multiple UDP virtual channels. 2022-01-28 10:11:45 +01:00
packet.py {De,P}acketizer: fix source.last assignment between the two FSMs 2021-10-28 15:35:12 +02:00