Florent Kermarrec fb478537e7 phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk. ... This makes it Xilinx specific, but without it ISE simplifies this as a single signal (which is fine) but is not able to keep track of the "keep" attribute of both signals and fails applying the constraints.		2020-03-25 12:40:02 +01:00
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core	A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead	2020-01-17 09:23:03 -08:00
frontend	global: keep up to date with LiteX (update stream_packet import to packet)	2019-11-21 11:01:50 +01:00
mac	mac: add crossbar for sharing PHY between HW ethernet cores and Wishbone	2020-03-13 15:30:36 +01:00
phy	phy/gmii: use a BUFG between eth_rx.clk and eth_rx.clk.	2020-03-25 12:40:02 +01:00
software	liteeth/software: remove libwip/libuip examples.	2019-06-17 21:17:52 +02:00
__init__.py	init repo	2015-09-07 13:29:34 +02:00
common.py	global: keep up to date with LiteX (update stream_packet import to packet)	2019-11-21 11:01:50 +01:00
crossbar.py	global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links	2019-11-21 11:01:55 +01:00
gen.py	liteeth_gen: improve readability and add clk_freq checks.	2020-03-19 19:58:35 +01:00