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litescope
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example_design: update with litex and fix

This commit is contained in:
Florent Kermarrec 2017-06-22 17:56:06 +02:00
parent e2cb7bd829
commit 01eabb2d0d
3 changed files with 10 additions and 9 deletions
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5
example_designs/make.py
View File

@ -94,6 +94,7 @@ if __name__ == "__main__":
try: try:
memory_regions = soc.get_memory_regions() memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions() csr_regions = soc.get_csr_regions()
csr_constants = soc.get_constants()
except: except:
pass pass
@ -117,7 +118,7 @@ if __name__ == "__main__":
/_/ /_/
A small footprint and configurable embedded FPGA A small footprint and configurable embedded FPGA
logic analyzer core powered by Migen logic analyzer core powered by LiteX
====== Building parameters: ======""") ====== Building parameters: ======""")
if hasattr(soc, "io"): if hasattr(soc, "io"):
@ -153,7 +154,7 @@ Depth: {}
subprocess.call(["rm", "-rf", "build/*"]) subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]: if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions) csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
write_to_file(args.csr_csv, csr_csv) write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]: if actions["build-core"]:

2
example_designs/targets/simple.py
View File

@ -36,8 +36,6 @@ class LiteScopeSoC(SoCCore):
counter = Signal(16) counter = Signal(16)
self.sync += counter.eq(counter + 1) self.sync += counter.eq(counter + 1)
toto = Signal()
self.submodules.analyzer = LiteScopeAnalyzer(counter, 512) self.submodules.analyzer = LiteScopeAnalyzer(counter, 512)
def do_exit(self, vns): def do_exit(self, vns):

12
example_designs/test/test_regs.py
View File

@ -5,11 +5,13 @@ wb.open()
# # # # # #
identifier = "" fpga_id = ""
for i in range(30): for i in range(256):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1? c = chr(wb.read(wb.bases.identifier_mem + 4*i) & 0xff)
print(identifier) fpga_id += c
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000)) if c == "\0":
break
print(fpga_id)
# # # # # #