core/_Storage: Simplify/Fix w_conv.sink.data assignement.
- Constant(0, pads_bits) breaks cases where pads_bits==0. - Assignement of MSBs to 0 is implicit.
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@ -227,7 +227,7 @@ class _Storage(Module, AutoCSR):
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pad_bits = - data_width % read_width
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pad_bits = - data_width % read_width
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self.submodules.w_conv = w_conv = stream.Converter(data_width + pad_bits, read_width)
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self.submodules.w_conv = w_conv = stream.Converter(data_width + pad_bits, read_width)
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self.comb += [
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self.comb += [
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self.w_conv.sink.data.eq(Cat(cdc.source.data, Constant(0, pad_bits))),
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self.w_conv.sink.data.eq(cdc.source.data),
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self.w_conv.sink.valid.eq(cdc.source.valid),
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self.w_conv.sink.valid.eq(cdc.source.valid),
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cdc.source.ready.eq(self.w_conv.sink.ready),
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cdc.source.ready.eq(self.w_conv.sink.ready),
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]
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]
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