core/Trigger: also apply mask to trigger value (avoid having doing it in software).
This commit is contained in:
parent
12be70325e
commit
219a90122f
|
@ -80,7 +80,7 @@ class _Trigger(Module, AutoCSR):
|
||||||
self.submodules += flush
|
self.submodules += flush
|
||||||
self.comb += [
|
self.comb += [
|
||||||
flush.wait.eq(~(~enable & enable_d)), # flush when disabling
|
flush.wait.eq(~(~enable & enable_d)), # flush when disabling
|
||||||
hit.eq((sink.data & mem.source.mask) == mem.source.value),
|
hit.eq((sink.data & mem.source.mask) == (mem.source.value & mem.source.mask)),
|
||||||
mem.source.ready.eq((enable & hit) | ~flush.done),
|
mem.source.ready.eq((enable & hit) | ~flush.done),
|
||||||
]
|
]
|
||||||
|
|
||||||
|
@ -92,7 +92,6 @@ class _Trigger(Module, AutoCSR):
|
||||||
source.hit.eq(done)
|
source.hit.eq(done)
|
||||||
]
|
]
|
||||||
|
|
||||||
|
|
||||||
class _SubSampler(Module, AutoCSR):
|
class _SubSampler(Module, AutoCSR):
|
||||||
def __init__(self, data_width):
|
def __init__(self, data_width):
|
||||||
self.sink = sink = stream.Endpoint(core_layout(data_width))
|
self.sink = sink = stream.Endpoint(core_layout(data_width))
|
||||||
|
|
|
@ -80,7 +80,7 @@ class LiteScopeAnalyzerDriver:
|
||||||
if cond is not None:
|
if cond is not None:
|
||||||
for k, v in cond.items():
|
for k, v in cond.items():
|
||||||
value |= getattr(self, k + "_o")*v
|
value |= getattr(self, k + "_o")*v
|
||||||
mask |= getattr(self, k + "_m")
|
mask |= getattr(self, k + "_m")
|
||||||
self.trigger_mem_mask.write(mask)
|
self.trigger_mem_mask.write(mask)
|
||||||
self.trigger_mem_value.write(value)
|
self.trigger_mem_value.write(value)
|
||||||
self.trigger_mem_write.write(1)
|
self.trigger_mem_write.write(1)
|
||||||
|
|
Loading…
Reference in New Issue