core/Trigger: also apply mask to trigger value (avoid having doing it in software).
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@ -80,7 +80,7 @@ class _Trigger(Module, AutoCSR):
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self.submodules += flush
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self.comb += [
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flush.wait.eq(~(~enable & enable_d)), # flush when disabling
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hit.eq((sink.data & mem.source.mask) == mem.source.value),
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hit.eq((sink.data & mem.source.mask) == (mem.source.value & mem.source.mask)),
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mem.source.ready.eq((enable & hit) | ~flush.done),
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]
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@ -92,7 +92,6 @@ class _Trigger(Module, AutoCSR):
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source.hit.eq(done)
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]
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class _SubSampler(Module, AutoCSR):
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def __init__(self, data_width):
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self.sink = sink = stream.Endpoint(core_layout(data_width))
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@ -80,7 +80,7 @@ class LiteScopeAnalyzerDriver:
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if cond is not None:
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for k, v in cond.items():
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value |= getattr(self, k + "_o")*v
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mask |= getattr(self, k + "_m")
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mask |= getattr(self, k + "_m")
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self.trigger_mem_mask.write(mask)
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self.trigger_mem_value.write(value)
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self.trigger_mem_write.write(1)
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