core: add full flag for trigger memory
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@ -38,6 +38,7 @@ class FrontendTrigger(Module, AutoCSR):
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self.mem_write = CSR()
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self.mem_write = CSR()
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self.mem_mask = CSRStorage(dw)
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self.mem_mask = CSRStorage(dw)
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self.mem_value = CSRStorage(dw)
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self.mem_value = CSRStorage(dw)
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self.mem_full = CSRStatus()
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# # #
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# # #
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@ -58,7 +59,8 @@ class FrontendTrigger(Module, AutoCSR):
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self.comb += [
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self.comb += [
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mem.sink.valid.eq(self.mem_write.re),
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mem.sink.valid.eq(self.mem_write.re),
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mem.sink.mask.eq(self.mem_mask.storage),
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mem.sink.mask.eq(self.mem_mask.storage),
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mem.sink.value.eq(self.mem_value.storage)
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mem.sink.value.eq(self.mem_value.storage),
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self.mem_full.status.eq(~mem.sink.ready)
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]
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]
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# hit and memory read/flush
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# hit and memory read/flush
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