Fix: 2 signals in the storage class belong to the wrong clock domain

Signals & Domain overview:
  - self.{offset,length}.storage belong to sys clock
  - offset, length belong to scope clock
  - mem belongs to scope clock

Therefore, everything that involves mem needs to use offset/length
This commit is contained in:
Christian Klarhorst 2020-08-07 13:56:06 +02:00
parent 2ad73a0f54
commit ad4e46c8c6
1 changed files with 2 additions and 2 deletions

View File

@ -208,11 +208,11 @@ class _Storage(Module, AutoCSR):
If(sink.valid & sink.hit, If(sink.valid & sink.hit,
NextState("RUN") NextState("RUN")
), ),
mem.source.ready.eq(mem.level >= self.offset.storage) mem.source.ready.eq(mem.level >= offset)
) )
fsm.act("RUN", fsm.act("RUN",
sink.connect(mem.sink, omit={"hit"}), sink.connect(mem.sink, omit={"hit"}),
If(mem.level >= self.length.storage, If(mem.level >= length,
NextState("IDLE"), NextState("IDLE"),
) )
) )