Fix: 2 signals in the storage class belong to the wrong clock domain
Signals & Domain overview: - self.{offset,length}.storage belong to sys clock - offset, length belong to scope clock - mem belongs to scope clock Therefore, everything that involves mem needs to use offset/length
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@ -208,11 +208,11 @@ class _Storage(Module, AutoCSR):
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If(sink.valid & sink.hit,
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If(sink.valid & sink.hit,
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NextState("RUN")
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NextState("RUN")
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),
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),
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mem.source.ready.eq(mem.level >= self.offset.storage)
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mem.source.ready.eq(mem.level >= offset)
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)
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)
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fsm.act("RUN",
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fsm.act("RUN",
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sink.connect(mem.sink, omit={"hit"}),
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sink.connect(mem.sink, omit={"hit"}),
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If(mem.level >= self.length.storage,
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If(mem.level >= length,
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NextState("IDLE"),
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NextState("IDLE"),
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)
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)
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)
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)
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