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Merge pull request #16 from zyp/sigrok_width 

software/dump/sigrok: Support width > 1.
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enjoy-digital 2020-02-26 22:12:14 +01:00 committed by GitHub
parent 9dd2e968e9 e07bdbfb29
commit b3d1e6938f
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 13 additions and 6 deletions
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19
litescope/software/dump/sigrok.py
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@ -23,7 +23,7 @@ class SigrokDump(Dump):
f.close()
def write_metadata(self, name):
probe_bits = math.ceil(len(self.variables)/8)*8
probe_bits = math.ceil(sum(variable.width for variable in self.variables)/8)*8
f = open("metadata", "w")
r = """
[global]
@ -38,13 +38,20 @@ unitsize={}
self.samplerate//1e6*2,
probe_bits//8
)
for i, variable in enumerate(self.variables):
r += "probe{}={}\n".format(i + 1, variable.name)
i = 1
for variable in self.variables:
if variable.width > 1:
for j in range(variable.width):
r += "probe{}={}[{}]\n".format(i, variable.name, j)
i += 1
else:
r += "probe{}={}\n".format(i, variable.name)
i += 1
f.write(r)
f.close()
def write_data(self):
data_bits = math.ceil(len(self.variables)/8)*8
data_bits = math.ceil(sum(variable.width for variable in self.variables)/8)*8
data_len = 0
for variable in self.variables:
data_len = max(data_len, len(variable))
@ -52,9 +59,9 @@ unitsize={}
for i in range(data_len):
data = 0
for j, variable in enumerate(reversed(self.variables)):
data = data << 1
data = data << variable.width
try:
data |= variable.values[i] & 0x1 # 1 bit probes
data |= variable.values[i]
except:
pass
datas.append(data)