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core: add FSM support (and example)
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2 changed files with 17 additions and 0 deletions
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@ -59,6 +59,19 @@ class LiteScopeSoC(SoCCore):
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self.cpu_or_bridge.wishbone
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]
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# fsm group
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fsm = FSM(reset_state="STATE1")
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self.submodules += fsm
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fsm.act("STATE1",
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NextState("STATE2")
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)
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fsm.act("STATE2",
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NextState("STATE1")
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)
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analyzer_groups[2] = [
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fsm
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]
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# analyzer
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_groups, 512)
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@ -274,6 +274,10 @@ class LiteScopeAnalyzer(Module, AutoCSR):
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for s in signals:
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if isinstance(s, Record):
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split_signals.extend(s.flatten())
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elif isinstance(s, FSM):
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s.do_finalize()
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s.finalized = True
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split_signals.append(s.state)
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else:
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split_signals.append(s)
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new_groups[n] = split_signals
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